HI5628INZ Intersil, HI5628INZ Datasheet
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HI5628INZ
Specifications of HI5628INZ
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HI5628INZ Summary of contents
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... All other trademarks mentioned are the property of their respective owners. HI5628 FN4520.5 HI5628 (LQFP) TOP VIEW Intersil (and design registered trademark of Intersil Americas Inc. Copyright © Intersil Americas Inc. 2004. All Rights Reserved QD4 QD3 QD2 QD1 QD0 (LSB) DGND DGND DV DD DGND AGND ...
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Typical Applications Circuit 50Ω ID4 ID3 ID2 ID1 ID0 (LSB) SLEEP DV DD 0.1µ 0.1µ 0.1µF FERRITE +5V TO +3V POWER SUPPLY BEAD 10µH 10µF NOTE: Recommended separate analog and digital ground planes, connected at a ...
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Functional Block Diagram (LSB) ID0 ID1 ID2 ID3 LATCH ID4 ID5 ID6 (MSB) ID7 ICLK INT/EXT INT/EXT VOLTAGE REFERENCE REFERENCE SELECT REFLO REFIO FSADJ SLEEP (LSB) QD0 QD1 QD2 QD3 LATCH QD4 QD5 QD6 (MSB) QD7 QCLK AV AGND DV ...
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Absolute Maximum Ratings Digital Supply Voltage DV to DCOM . . . . . . . . . . . . . . . . . . +5.5V DD Analog Supply Voltage AV to ACOM . . . . . ...
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Electrical Specifications per channel except for ‘Power Supply Characteristics.’ (Continued) PARAMETER AC CHARACTERISTICS - HI5628IN - 125MHz (Per Channel) Spurious Free Dynamic Range, SFDR Within a Window Total Harmonic Distortion (THD) to Nyquist f Spurious Free Dynamic ...
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Electrical Specifications per channel except for ‘Power Supply Characteristics.’ (Continued) PARAMETER Data Setup Time Data Hold Time, t HLD Propagation Delay Time CLK Pulse Width PW1 PW2 POWER SUPPLY CHARACTERISTICS ...
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Timing Diagrams CLK D7-D0 I OUT t SETT t PD FIGURE 1. OUTPUT SETTLING TIME DIAGRAM CLK t SU D7-D0 I OUT t PD FIGURE 3. PROPAGATION DELAY, SETUP TIME, HOLD TIME AND MINIMUM PULSE WIDTH DIAGRAM 7 HI5628 50% ...
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Definition of Specifications Integral Linearity Error, INL, is the measure of the worst case point that deviates from a best fit straight line of data values along the transfer curve. Differential Linearity Error, DNL, is the measure of the step ...
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Digital Inputs and Termination The HI5628 digital inputs are guaranteed to CMOS levels. However, TTL compatibility can be achieved by lowering the supply voltage to 3V due to the digital threshold of the input buffer being approximately half of the ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...