HI5628INZ Intersil, HI5628INZ Datasheet - Page 9

• Manufacturer Part Number: HI5628INZ
• Description: IC DAC 8BIT 125MSPS DUAL 48-LQFP
• Manufacturer: Intersil

Specifications of HI5628INZ

• Number Of Bits: 8
• Data Interface: Parallel
• Number Of Converters: 2
• Voltage Supply Source: Analog and Digital
• Power Dissipation (max): 330mW
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Settling Time: -

Digital Inputs and Termination
The HI5628 digital inputs are guaranteed to CMOS levels.
However, TTL compatibility can be achieved by lowering the
supply voltage to 3V due to the digital threshold of the input
buffer being approximately half of the supply voltage. The
internal register is updated on the rising edge of the clock. To
minimize reflections, proper termination should be
implemented. If the lines driving the clock and the digital
inputs are 50Ω lines, then 50Ω termination resistors should be
placed as close to the converter inputs as possible, connected
to the digital ground plane (if separate grounds are used).
Ground Plane(s)
If separate digital and analog ground planes are used, then all
of the digital functions of the device and their corresponding
components should be over the digital ground plane and
terminated to the digital ground plane. The same is true for the
analog components and the analog ground plane. The
converter will function properly with a single ground plane, as
the Evaluation Board is configured in this matter.
Noise Reduction
To minimize power supply noise, 0.1µF capacitors should be
placed as close as possible to the converter’s power supply
pins, AV
using separate digital and analog ground planes, these
capacitors should be terminated to the digital ground for
DV
of the power supplies on the board is recommended.
Voltage Reference
The internal voltage reference of the device has a nominal
value of +1.2V with a ± 60 ppm /
temperature range of the converter. It is recommended that a
0.1µF capacitor be placed as close as possible to the REFIO
pin, connected to the analog ground. The REFLO pin (15)
selects the reference. The internal reference can be selected if
pin 15 is tied low (ground). If an external reference is desired,
then pin 15 should be tied high (to the analog supply voltage)
and the external reference driven into REFIO, pin 23. The full
scale output current of the converter is a function of the voltage
reference used and the value of R
the 2mA to 20mA range, through operation below 2mA is
possible, with performance degradation.
If the internal reference is used, V
approximately 1.16V (pin 22). If an external reference is used,
V
I
I
If the full scale output current is set to 20mA by using the
internal voltage reference (1.16V) and a 1.86kΩ R
resistor, then the input coding to output current will resemble
the following:
OUT
OUT
FSADJ
DD
(Full Scale) is:
(Full Scale) = (V
and to the analog ground for AV
DD
will equal the external reference. The calculation for
and DV
DD
FSADJ
. Also, should the layout be designed
/R
9
o
SET
C drift coefficient over the full
SET
FSADJ
) x 32.
. I
DD
OUT
will equal
. Additional filtering
should be within
SET
HI5628
Outputs
IOUTA and IOUTB (or QOUTA and QOUTB) are
complementary current outputs. The sum of the two currents
is always equal to the full scale output current minus one
LSB. If single ended use is desired, a load resistor can be
used to convert the output current to a voltage. It is
recommended that the unused output be either grounded or
equally terminated. The voltage developed at the output
must not violate the output voltage compliance range of
-0.3V to 1.25V. R
output voltage is produced in conjunction with the output full
scale current, which is described above in the ‘Reference’
section. If a known line impedance is to be driven, then the
output load resistor should be chosen to match this
impedance. The output voltage equation is:
V
These outputs can be used in a differential-to-single-ended
arrangement to achieve better harmonic rejection. The
SFDR measurements in this data sheet were performed with
a 1:1 transformer on the output of the DAC (see Figure 1).
With the center tap grounded, the output swing of pins 16
and 17 will be biased at zero volts. It is important to note
here that the negative voltage output compliance range limit
is -300mV, imposing a maximum of 600mV
with this configuration. The loading as shown in Figure 1 will
result in a 500mV signal at the output of the transformer if
the full scale output current of the DAC is set to 20mA.
V
Allowing the center tap to float will result in identical
transformer output, however the output pins of the DAC will
have positive DC offset. The 50Ω load on the output of the
transformer represents the spectrum analyzer’s input
impedance.
OUT
OUT
INPUT CODE (D7-D0)
PIN 17 (20)
PIN 16 (21)
= I
= 2 x I
1000 0000
0000 0000
TABLE 1. INPUT CODING vs OUTPUT CURRENT
1111 1111
OUT
IOUTB (QOUTB)
OUT
IOUTA (QOUTA)
X R
LOAD
x R
LOAD
EQ ,
should be chosen so that the desired
.
where R
FIGURE 4.
100Ω
IOUTA (mA)
50Ω
50Ω
20
10
0
EQ
V
is ~12.5Ω .
OUT
= (2 x I
P-P
50Ω
IOUTB (mA)
amplitude
OUT
10
20
0
x R
EQ
)V