AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 101

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

7-6
5
4
3
2
1
0
RCVCCOM
TXSTRTM
RCVCCO
TXSTRT
JABM
RES
JAB
MFCOM is set by Reset and is
not affected by STOP.
Reserved locations. Read and
written as zero.
Receive Collision Counter Over-
flow.
This bit indicates the Receive
Collision Counter (CSR114) has
overflowed. It can be cleared by
writing a 1 to this bit. Also
cleared by RESET or setting the
STOP bit. Writing a 0 has no
effect.
Receive Collision Counter Over-
flow Mask.
If RCVCCOM is set, RCVCCO
will not set INTR in CSR0.
RCVCCOM is set by RESET
and is not affected by STOP.
Transmit Start status is set when-
ever
begins transmission of a frame.
When TXSTRT is set, IRQ is
asserted if IENA = 1 and the
mask bit TXSTRTM (CSR4.2) is
clear.
TXSTRT is set by the MAC Unit
and cleared by writing a “1", set-
ting RESET or setting the STOP
bit. Writing a “0" has no effect.
Transmit
TXSTRTM is set, the TXSTRT bit
in CSR4 will be masked and will
not set INTR flag in CSR0.
TXSTRTM is set by RESET and
is not affected by STOP.
Jabber Error is set when the
PCnet-ISA II controller Twist-
ed-pair MAU function exceeds
an allowed transmission limit.
Jabber is set by the TMAU cir-
cuit and can only be asserted in
10BASE-T mode.
When JAB is set, IRQ is assert-
ed if IENA = 1 and the mask bit
JABM (CSR4.4) is clear.
The JAB bit can be reset even if
the jabber condition is still
present.
JAB is set by the TMAU circuit
and cleared by writing a “1".
Writing a “0" has no effect. JAB
is also cleared by RESET or set-
ting the STOP bit.
Jabber Error Mask. If JABM is
set, the JAB bit in CSR4 will be
masked and will not set INTR
flag in CSR0.
PCnet-ISA
Start
II
Mask.
controller
Am79C961A
If
CSR5: Control 1
Bit
0
SPND
Name
JABM is set by RESET and is
not affected by STOP.
Suspend. Setting SPND to ONE
will cause the PCnet-ISA II con-
troller to start entering the sus-
pend mode. The host must poll
SPND until it reads a ONE back,
to determine that the PCnet-ISA
II controller has entered the sus-
pend mode. Setting SPND to
ZERO will get the PCnet-ISA II
controller out of suspend mode
and back into its active state.
SPND can only be set to ONE if
STOP (CSR0, bit 2) is set to
ZERO. Asserting the RESET
pin, reading the RESET register,
or setting the STOP bit forces
the PCnet-ISA II controller out of
suspend mode.
When the host requests the PC-
net-ISA II controller to enter the
suspend mode, the device first
finishes all on-going transmit
activity
tor entries. It then completes
any frame reception occurring
at the time the SPND bit was
set, and updates the corre-
sponding receive descriptor en-
tries. Any subsequent frames
incident upon the PCnet-ISA II
during suspend mode will not
be received, nor will any notifi-
cation be given as to the missed
frames (the MISS bit in CSR0
will not be updated while in sus-
pend mode). It then sets the
read-version of SPND to ONE
and enters the suspend mode.
In suspend mode, all of the
CSR registers are accessible.
As long as the PCnet-ISA II
controller is not reset while in
suspend mode (by asserting the
RESET pin, reading the RESET
register, or setting the STOP
bit), no reinitialization of the
mode. The PCnet-ISA II control-
ler will continue at the transmit
and receive descriptor ring
when it entered the suspend
mode.
corresponding transmit descrip-
device is required after the
device comes out of suspend
locations, where it had left,
and
Description
updates
101
the