AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 93

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

Receive FCS Checking
Reception and checking of the received FCS is per-
formed automatically by the PCnet-ISA II controller.
Note that if the Automatic Pad Stripping feature is
enabled, the received FCS will be verified against the
value computed for the incoming bit stream including
pad characters, but it will not be passed to the host. If
a FCS error is detected, this will be reported by the
CRC bit in RMD1.
Receive Exception Conditions
Exception conditions for frame reception fall into two
distinct categories; those which are the result of normal
network operation, and those which occur due to
abnormal network and/or host related events.
Normal events which may occur and which are handled
autonomously by the PCnet-ISA II controller are basi-
cally collisions within the slot time and automatic runt
packet rejection. The PCnet-ISA II controller will ensure
that collisions which occur within 512 bit times from the
start of reception (excluding preamble) will be automat-
ically deleted from the receive FIFO with no host inter-
vention. The receive FIFO will delete any frame which
is composed of fewer than 64 bytes provided that the
Runt Packet Accept (RPA bit in CSR124) feature has
not been enabled. This criteria will be met regardless of
whether the receive frame was the first (or only) frame
in the FIFO or if the receive frame was queued behind
a previously received message.
Abnormal network conditions include:
1010....1010
Preamble
Bits
56
Increasing Time
Start of Packet
at Time= 0
10101011
IEEE/ANSI 802.3 Frame and Length Field Transmission Order
SYNCH
Bits
8
ADDR.
Bytes
Dest.
6
Am79C961A
ADDR.
Bit
Bytes
0
Srce.
Significant
6
Most
Byte
These should not occur on a correctly configured 802.3
network and will be reported if they do.
Host related receive exception conditions include
MISS, BUFF, and OFLO. These are described in the
Receive Descriptor section.
Loopback Operation
Loopback is a mode of operation intended for system
diagnostics. In this mode, the transmitter and receiver
are both operating at the same time so that the
controller receives its own transmissions. The control-
ler provides two types of internal loopback and three
types of external loopback. In internal loopback mode,
the transmitted data can be looped back to the receiver
at one of two places inside the controller without actu-
ally transmitting any data to the external network. The
receiver will move the received data to the next receive
buffer, where it can be examined by software. Alterna-
tively, external loopback causes transmissions to go
off-chip. For the AUI port, frame transmission occurs
normally and assumes that an external MAU will loop
the frame back to the chip. For the 10BASE-T port, two
external loopback options are available, both of which
require a valid link pass state and both of which trans-
mit data frames at the RJ45 interface. Selection of
these modes is defined by the TMAU_LOOPE bit in
ISACSR2. One option loops the data frame back inside
the chip, and is compatible with a ‘live’ network. The
FCS errors
Late collision
Length
Bit
Bytes
7
2
Bit
0
Significant
Least
Byte
1–1500
Bytes
DATA
LLC
Bit
7
Bytes
Bytes
45–0
Pad
Bytes
FCS
4
19364B-21
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