AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 89

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

The only way to configure the PCnet-ISA II controller
for 8-bit ISA bus cycles for SRAM accesses is to con-
figure the entire PCnet-ISA II controller to support only
8-bit ISA bus cycles. This is accomplished by leaving
the SBHE pin disconnected. The PCnet-ISA II control-
ler will perform 8-bit ISA bus cycle operation for all
resources (registers, PROMs, SRAM) if SBHE has
never been driven active since the last RESET, such as
in the case of an 8-bit system like the PC/XT. In this
case, the external address decode logic must not
assert MEMCS16 to the ISA bus, which will be the case
if MEMCS16 is left unconnected. It is possible to man-
ufacture a dual 8/16 bit PCnet-ISA II controller adapter
card, as the MEMCS16 and SBHE signals do not exist
in the PC/XT environment.
At the memory device level, each SRAM Private Bus
read cycle takes two 50 ns clock periods for a maxi-
mum read access time of 75 ns. The timing looks like
this:
The address and SROE go active within 20 ns of the
clock going HIGH. Data is required to be valid 5 ns
before the end of the second clock cycle. Address and
SROE have a 0 ns hold time after the end of the second
clock cycle. Note that the PCnet-ISA II controller does
not normally provide a separate SRAM CS signal;
SRAM CS must always be asserted.
SRAM Private Bus write cycles require three 50 ns
clock periods to guarantee non-negative address setup
and hold times with regard to SRWE. The timing is
illustrated as follows:
(20 MHz)
Address
(20 MHz)
Address/
XTAL1
XTAL1
SROE
SRWE
Data
Static
Static RAM Read Cycle
19364B-19
19364B-18
Am79C961A
Address and data are valid 20 ns after the rising edge
of the first clock period. SRWE goes active 20 ns after
the falling edge of the first clock period. SRWE goes
inactive 20 ns after the falling edge of the third clock
period. Address and data remain valid until the end of
the third clock period. Rise and fall times are nominally
5 ns. Non-negative setup and hold times for address
and data with respect to SRWE are guaranteed. SRWE
has a pulse width of typically 100 ns, minimum 75 ns.
Static RAM Cycles – Programmed I/O Architecture
In the Programmed I/O Architecture mode, the SRAM
is an 8-bit device connected to the PCnet-ISA II con-
troller Private Bus, and can occupy up to 64 Kbytes of
address space. The SRAM is accessed through the
ISACSR0 and ISACSR1 registers which serve as the
SRAM Data port and SRAM Address pointer, respec-
tively. Since the ISACSRs are used to access the
SRAM, simple I/O accesses (to RAP and IDP) which
are decoded by the PCnet-ISA II are used to access
the SRAM without any external decoding logic.
The RAP and IDP ports are naturally 16-bit resources
and can be accessed with 16-bit ISA I/O cycles if the
IO_MODE bit (PnP 0xF0) is set. As discussed in the
Ethernet Controller Register Cycles section, 8-bit I/O
cycles are also allowed, provided the proper protocol is
followed. This protocol requires that byte accesses
must be performed in pairs, with the even byte access
always being followed by associated odd byte access.
In the Programmed I/O architecture mode, when
a c c e s s i n g t h e S R A M D a t a Po r t i n p a r t i c u l a r
(ISACSR0), the restrictions on byte accesses are
slightly different. Even byte accesses (accesses where
A0 = 0, SBHE = 1) may be performed to ISACSR0 with-
out any restriction. A corresponding odd byte access
need not be performed following the even byte access
as is required when accessing all other controller reg-
isters. In fact, odd byte accesses (accesses where A0
= 1, SBHE = 1) may not be performed to ISACSR0, ex-
cept when they are the result of a software 16-bit
access that are automatically converted to two byte ac-
cesses by motherboard logic.
Since the internal PCnet-ISA II registers are used to
access the SRAM in the Programmed I/O architecture
mode, the access cycle on the ISA bus is identical to
that described in the Ethernet Controller Register
Cycles section.
To minimize the number of I/O cycles required to
access the SRAM, the PCnet-ISA II auto-increments
the SRAM Address Pointer (ISACSR1) by one or two
following every read or write to the SRAM Data Port
(ISACSR0). If a single byte read or write to the SRAM
Data Port occurs, the SRAM Address Pointer is auto-
matically incremented by 1. If a word read or write to
the SRAM Data Port occurs, the SRAM Address
Pointer is automatically incremented by 2. This allows
89