AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 106

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

CSR22-23: Next Receive Buffer Address
Bit
31-24
23-0
CSR24-25: Base Address of Receive Ring
Bit
31-24
23-0
CSR26-27: Next Receive Descriptor Address
Bit
31-24
23-0
CSR28-29: Current Receive Descriptor Address
Bit
31-24
23-0
CSR30-31: Base Address of Transmit Ring
Bit
31-24
23-0
106
BADR
NRDA
CRDA
NRBA
BADX
Name
Name
Name
Name
Name
RES
RES
RES
RES
RES
Reserved locations. Written as
zero and read as undefined.
Contains the next receive buffer
address to which the PCnet-ISA
II controller will store incoming
frame data.
Read/write
when STOP or SPND bits are
set.
Reserved locations. Written as
zero and read as undefined.
Contains the base address of
the Receive Ring.
Read/write
when STOP or SPND bits are
set.
Reserved locations. Written as
zero and read as undefined.
Contains
address pointer.
Read/write
when STOP or SPND bits are
set.
Reserved locations. Written as
zero and read as undefined.
Contains the current RDRE
address pointer.
Read/write
when STOP or SPND bits are
set.
Reserved locations. Written as
zero and read as undefined.
Contains the base address of
the Transmit Ring.
Description
Description
Description
Description
Description
the
accessible
accessible
accessible
accessible
next
RDRE
only
only
only
only
Am79C961A
CSR32-33: Next Transmit Descriptor Address
Bit
31-24
23-0
CSR34-35: Current Transmit Descriptor Address
Bit
31-24
23-0
CSR36-37: Next Next Receive Descriptor Address
Bit
31-0
CSR38-39: Next Next Transmit Descriptor Address
Bit
31-0
CSR40-41: Current Receive Status and Byte Count
Bit
31-24 CRST
23-12
NNRDA
NNXDA
CXDA
NXDA
Name
Name
Name
Name
Name
RES
RES
RES
Read/write
when STOP or SPND bits are
set.
Reserved locations. Written as
zero and read as undefined.
Contains the next TDRE address
pointer.
Read/write
when STOP or SPND bits are
set.
Reserved locations. Written as
zero and read as undefined.
Contains the current TDRE
address pointer.
Read/write
when STOP or SPND bits are
set.
Contains the next next RDRE
address pointer.
Read/write
when STOP or SPND bits are
set.
Contains the next next TDRE
address pointer.
Read/write
when STOP or SPND bits are
set.
Current Receive Status. This
field is a copy of bits 15:8 of
RMD1 of the current receive
descriptor.
Read/write
when STOP or SPND bits are
set.
Reserved locations. Written as
zero and read as undefined.
Description
Description
Description
Description
Description
accessible
accessible
accessible
accessible
accessible
accessible
only
only
only
only
only
only