AM79C961AVIW AMD (ADVANCED MICRO DEVICES), AM79C961AVIW Datasheet - Page 65

• Manufacturer Part Number: AM79C961AVIW
• Manufacturer: AMD (ADVANCED MICRO DEVICES)

Specifications of AM79C961AVIW

• Operating Supply Voltage (typ): 5V
• Operating Supply Voltage (min): 4.75V
• Operating Supply Voltage (max): 5.25V
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 144
• Lead Free Status / Rohs Status: Not Compliant

plete word may become available before the end of the
arbitration cycle and thereby increase the number of
transfers in that cycle. The general rule is that the
longer the Bus Grant latency or the slower the bus
transfer operations (or clock speed) or the higher the
transmit watermark or the lower the receive watermark
or any combination thereof, the longer will be the aver-
age bus mastership period.
Buffer Management Unit (BMU)
The buffer management unit is a microcoded 20 MHz
state machine which implements the initialization block
and the descriptor architecture.
Initialization
PCnet-ISA II controller initialization includes the read-
ing of the initialization block in memory to obtain the
operating parameters. The initialization block is read
when the INIT bit in CSR0 is set. The INIT bit should be
set before or concurrent with the STRT bit to insure cor-
rect operation. See previous section “1. Initialization
Block DMA Transfer.” Once the initialization block has
been read in and processed, the BMU knows where the
receive and transmit descriptor rings are. On comple-
tion of the read operation and after internal registers
have been updated, IDON will be set in CSR0, and an
interrupt generated if IENA is set.
The Initialization Block is vectored by the contents of
CSR1 (least significant 16 bits of address) and CSR2
(most significant 8 bits of address). The block contains
the user defined conditions for PCnet-ISA II controller
operation, together with the address and length infor-
mation to allow linkage of the transmit and receive
descriptor rings.
There is an alternative method to initialize the PC-
net-ISA II controller. Instead of initialization via the ini-
tialization block in memory, data can be written directly
into the appropriate registers. Either method may be
used at the discretion of the programmer. If the regis-
ters are written to directly, the INIT bit must not be set,
or the initialization block will be read in, thus overwriting
the previously written information. Please refer to
Appendix D for details on this alternative method.
Reinitialization
The transmitter and receiver section of the PCnet-ISA
II controller can be turned on via the initialization block
(MODE Register DTX, DRX bits; CSR15[1:0]). The
state of the transmitter and receiver are monitored
through CSR0 (RXON, TXON bits). The PCnet-ISA II
controller should be reinitialized if the transmitter and/
or the receiver were not turned on during the original
initialization and it was subsequently required to acti-
vate them, or if either section shut off due to the detec-
tion of an error condition (MERR, UFLO, TX BUFF
error).
Am79C961A
Reinitialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing
to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same
in the PCnet-ISA II controller as in the LANCE. In par-
ticular, the PCnet-ISA II controller reloads the transmit
and receive descriptor pointers (working registers) with
their respective base addresses. This means that the
software must clear the descriptor’s own bits and reset
its descriptor ring pointers before the restart of the PC-
net-ISA controller. The reload of descriptor base
addresses is performed in the LANCE only after initial-
ization, so a restart of the LANCE without initialization
leaves the LANCE pointing at the same descriptor
locations as before the restart.
Suspend
The PCnet-ISA II controller offers a suspend mode that
allows easy updating of the CSR registers without
going through a full reinitialization of the device. The
suspend mode also allows stopping the device with
orderly termination of all network activity.
The host requests the PCnet-ISA II controller to enter
the suspend mode by setting SPND (CSR5, bit 0) to
ONE. The host must poll SPND until it reads back ONE
to determine that the PCnet-ISA II controller has en-
tered the suspend mode. When the host sets SPND to
ONE, the PCnet-ISA II controller first finishes all on-go-
ing transmit activity and updates the corresponding
transmit descriptor entries. It then finishes all on-going
receive activity and updates the corresponding receive
descriptor entries. It then sets the read-version of
SPND to ONE and enters the suspend mode. In sus-
pend mode, all of the CSR registers are accessible. As
long as the PCnet-ISA II controller is not reset while in
suspend mode (by asserting the RESET pin, reading
the RESET register, or by setting the STOP bit), no
reinitialization of the device is required after the device
comes out of suspend mode. When SPND is set to
ZERO, the PCnet-ISA II controller will leave the sus-
pend mode and will continue at the transmit and re-
ceive descriptor ring locations where it had left when it
entered the suspend mode.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in mem-
ory. There are two rings, a receive ring and a transmit
ring. The size of a message descriptor entry is 4 words
(8 bytes).
Descriptor Rings
Each descriptor ring must be organized in a contiguous
area of memory. At initialization time (setting the INIT
bit in CSR0), the PCnet-ISA II controller reads the
user-defined base address for the transmit and receive
descriptor rings, which must be on an 8-byte boundary,
as well as the number of entries contained in the
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