SAA7324H NXP Semiconductors, SAA7324H Datasheet - Page 11

• Manufacturer Part Number: SAA7324H
• Manufacturer: NXP Semiconductors

Specifications of SAA7324H

• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.4
7.4.1
A double timing system is used to protect the demodulator
from erroneous sync patterns in the serial data.
The master counter is only reset if:
The sync coincidence signal is also used to generate the
PLL lock signal, which is active HIGH after 1 sync
coincidence is found, and reset LOW if during 61
consecutive frames no sync coincidence is found. The PLL
lock signal can be accessed via the SDA or STATUS pins
selected by decoder registers 2 and 7.
2000 Jun 26
A sync coincidence is detected; sync pattern occurs
588 1 EFM clocks after the previous sync pattern
A new sync pattern is detected within 6 EFM clocks of
its expected position.
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
Demodulator
F
RAME SYNC PROTECTION
HF input
Fig.6 Data slicer showing typical application components (for n = 1).
V SSA
100 nF
100 nF
22 k
1 nF
V SSA
2.2 k
47 pF
HFREF
ISLICE
HFIN
11
Also incorporated in the demodulator is a Run Length 2
(RL2) correction circuit. Every symbol detected as RL2 will
be pushed back to RL3. To do this, the phase error of both
edges of the RL2 symbol are compared and the correction
is executed at the side with the highest error probability.
7.4.2
The 14-bit EFM data and subcode words are decoded into
8-bit symbols.
100 A
100 A
EFM
D
crystal
clock
V SS
V DD
DEMODULATION
Q
DPLL
MGS179
Product specification
SAA7324