SAA7324H NXP Semiconductors, SAA7324H Datasheet - Page 33

• Manufacturer Part Number: SAA7324H
• Manufacturer: NXP Semiconductors

Specifications of SAA7324H

• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.15.1
7.15.1.1
The sixteen 4-bit programmable configuration registers,
0 to F (see Table 14), can be written to via the
microcontroller interface using the protocol shown in
Fig.23.
It should be noted that SILD must be held HIGH; A3 to A0
identifies the register number and D3 to D0 is the data.
The data is latched into the register on the LOW-to-HIGH
transition of RAB.
7.15.1.2
The same data can be repeated several times (e.g. for a
fade function) by applying extra RAB pulses as shown in
Fig.24. It should be noted that SCL must stay HIGH
between RAB pulses.
7.15.1.3
There are several internal status signals, selected via
register 2, which can be made available on the SDA line:
The status read protocol is shown in Fig.25. It should be
noted that SILD must be held HIGH.
2000 Jun 26
SUBQREADY-I: LOW if new subcode word is ready in
Q-channel register
MOTSTART1: HIGH if motor is turning at 75% or more
of nominal speed
MOTSTART2: HIGH if motor is turning at 50% or more
of nominal speed
MOTSTOP: HIGH if motor is turning at 12% or less of
nominal speed; can be set to indicate 6% or less
(instead of 12% or less) via register E
PLL lock: HIGH if sync coincidence signals are found
V1: follows input on pin V1
V2: follows input on pin V2
MOTOR-OV: HIGH if the motor servo output stage
saturates
FIFO-OV: HIGH if FIFO overflows
SHOCK: MOTSTART2 + PLL Lock + MOTOR-OV +
FIFO-OV + servo interrupt signal + OTD (HIGH if shock
detected)
LA-SHOCK: latched SHOCK signal.
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
M
ICROCONTROLLER INTERFACE
Writing data to registers 0 to F
Writing repeated data to registers 0 to F
Reading decoder status information on SDA
(4-
WIRE BUS MODE
)
33
7.15.1.4
To read the Q-channel subcode direct in the 4-wire bus
mode, the SUBQREADY-I signal should be selected as
status signal. The subcode read protocol is illustrated in
Fig.26.
It should be noted that SILD must be held HIGH; after
subcode read starts, the microcontroller may take as long
as it wants to terminate the read operation. When enough
subcode has been read (1 to 96 bits), terminate reading by
pulling RAB LOW.
Alternatively, the Q-channel subcode can be read using a
servo command as follows:
7.15.1.5
When the CRC of the Q-channel word is good, and no
subcode is being read, the SUBQREADY-I status signal
will react as shown in Fig.27. When the CRC is good and
the subcode is being read, the timing in Fig.28 applies.
If t
is below 2.6/n ms, then t
microcontroller can read all subcode frames if it completes
the read operation within 2.6/n ms after the subcode is
ready). If these criteria are not met, it is only possible to
guarantee that t
If subcode frames with failed CRCs are present, the
t
defective subcode frame.
It should be noted that in the lock-to-disc mode ‘n’ is
replaced by ‘d’, which is the disc speed factor.
7.15.1.6
A write data command is used to transfer data (a number
of bytes) from the microcontroller, using the protocol
shown in Fig.29. The first of these bytes is the command
byte and the following are data bytes; the number
(between 1 and 7) depends on the command byte.
2
and t
Use the read high-level status command to monitor the
subcode ready signal
Send the read subcode command and read the required
number of bytes (up to 12)
Send the read high-level status command; to re-enable
the decoder interface.
1
(SUBQREADY-I status LOW to end of subcode read)
3
times will be increased by 13.1/n ms for each
Reading Q-channel subcode
Behaviour of the SUBQREADY-I signal
Write servo commands
3
will be below 26.2/n ms (approximately).
2
= 13.1/n ms (i.e. the
Product specification
SAA7324