SAA7324H NXP Semiconductors, SAA7324H Datasheet - Page 9

• Manufacturer Part Number: SAA7324H
• Manufacturer: NXP Semiconductors

Specifications of SAA7324H

• Operating Temperature (max): 70C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 64
• Lead Free Status / Rohs Status: Compliant

Philips Semiconductors
7.1.3
For electronic shock absorption applications, the SAA7324
can be put into lock-to-disc mode. This allows Constant
Angular Velocity (CAV) disc playback with varying input
data rates from the inside-to-outside of the disc.
In the lock-to-disc mode, the FIFO is blocked and the
decoder will adjust its output data rate to the disc speed.
Hence, the frequency of the I
clocks are dependent on the disc speed. In the lock-to-disc
mode there is a limit on the maximum variation in disc
speed that the SAA7324 will follow. Disc speeds must
always be within 25% to 100% range of their nominal
value. The lock-to-disc mode is enabled/disabled by
decoder register E.
7.1.4
The SAA7324 may be placed in two standby modes
selected by decoder register B (it should be noted that the
device core is still active):
Table 1 Playback speeds
Notes
1. The CL11 output is always a 5.6448 MHz clock if a 16.9344 MHz external clock is used and SELPLL = 0. CL11 is
2. Data capture performance is not optimized for this option.
2000 Jun 26
REGISTER B
Standby 1: CD-STOP mode; most I/O functions are
switched off
Digital servo processor and Compact Disc
decoder with integrated DAC (CD10 II)
available on the CL11/4 output, enabled by programming shadow register 3 (see Section 7.15.3).
00XX
00XX
01XX
01XX
10XX
10XX
11XX
11XX
00XX
00XX
01XX
01XX
L
S
OCK
TANDBY MODES
-
TO
-
DISC MODE
REGISTER E
0XXX
0XXX
0XXX
0XXX
0XXX
0XXX
0XXX
0XXX
1XXX
1XXX
1XXX
1XXX
2
S-bus (WCLK and SCLK)
SELPLL
0
1
0
1
0
1
0
1
0
1
0
1
33.8688
CRYSTAL FREQUENCY (MHz)
n = 4
n = 1
n = 2
(2)
9
In the standby modes the various pins will have the
following values:
16.9344
n = 2
n = 4
Standby 2: CD-PAUSE mode; audio output features are
switched off, but the motor loop, the motor output and
the subcode interfaces remain active; this is also called
a ‘Hot Pause’.
MOTO1 and MOTO2: put in high-impedance, PWM
mode (standby 1 and reset: operating in standby 2); put
in high-impedance, PDM mode (standby 1 and reset:
operating in standby 2)
SCL and SDA: no interaction; normal operation
continues
SCLK, WCLK, DATA, EF and DOBM: 3-state in both
standby modes; normal operation continues after reset
CRIN, CROUT, CL16 and CL11/4: no interaction;
normal operation continues
V1, V2/V3, V4, V5 and CFLG: no interaction; normal
operation continues.
n = 1
n = 1
n = 2
n = 4
(2)
(2)
8.4672
n = 1
n = 2
n = 4
CL11 FREQUENCY (MHz)
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
11.2896
Product specification
5.6448
5.6448
5.6448
SAA7324
(1)