EP3C10E144C8N Altera, EP3C10E144C8N Datasheet - Page 122

• Manufacturer Part Number: EP3C10E144C8N
• Description: IC CYCLONE III FPGA 10K 144-EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C10E144C8N

• Number Of Logic Elements/cells: 10320
• Number Of Labs/clbs: 645
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 10320
• # I/os (max): 94
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 10320
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2427; EP3C10E144C8N

6–22
Table 6–7. Chapter Revision History (Part 2 of 3)
Cyclone III Device Handbook, Volume 1
May 2008
Date
Version
2.0
Changes include addition of BLVDS information.
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Added an introduction to “I/O Element Features” section.
Updated “Slew Rate Control” section.
Updated “Programmable Delay” section.
Updated Table 6–1 with BLVDS information.
Updated Table 6–2.
Updated “PCI-Clamp Diode” section.
Updated “LVDS Transmitter Programmable Pre-Emphasis” section.
Updated “On-Chip Termination with Calibration” section and added new
Figure 6–9.
Updated Table 6–3 title.
Updated Table 6–4 unit.
Updated “I/O Standards” section and Table 6–5 with BLVDS information and
added (Note 5).
Updated “Differential I/O Standard Termination” section with BLVDS
information.
Updated “I/O Banks” section.
Updated (Note 2) and added (Note 7) and BLVDS information to
Figure 6–15.
Updated (Note 2) and added BLVDS information to Table 6–6.
Added MBGA package information to Table 6–7.
Deleted Table 6-8.
Updated “High-Speed Differential Interfaces” section with BLVDS
information.
Updated “Differential Pad Placement Guidelines” section and added new
Figure 6–16.
Updated “V
Figure 6–17.
Updated Table 6–11.
Added new “DCLK Pad Placement Guidelines” section.
Updated “DC Guidelines” section.
REF
Pad Placement Guidelines” section and added new
Chapter 6: I/O Features in the Cyclone III Device Family
Changes Made
© December 2009 Altera Corporation
Chapter Revision History