EP3C10E144C8N Altera, EP3C10E144C8N Datasheet - Page 144

• Manufacturer Part Number: EP3C10E144C8N
• Description: IC CYCLONE III FPGA 10K 144-EQFP
• Manufacturer: Altera
• Series: Cyclone® IIIr

Specifications of EP3C10E144C8N

• Number Of Logic Elements/cells: 10320
• Number Of Labs/clbs: 645
• Total Ram Bits: 423936
• Number Of I /o: 94
• Voltage - Supply: 1.15 V ~ 1.25 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 144-EQFP
• Family Name: Cyclone III
• Number Of Logic Blocks/elements: 10320
• # I/os (max): 94
• Frequency (max): 402MHz
• Process Technology: 65nm
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 10320
• Ram Bits: 423936
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 144
• Package Type: EQFP
• For Use With: 544-2601 - KIT DEV CYCLONE III LS EP3CLS200544-2411 - KIT DEV NIOS II CYCLONE III ED.
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 544-2427; EP3C10E144C8N

7–20
Table 7–6. Chapter Revision History (Part 2 of 2)
Cyclone III Device Handbook, Volume 1
May 2008
July 2007
March 2007
Date
Version
1.2
1.1
1.0
Changes include addition of BLVD information
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Initial release.
Updated “Introduction” section with BLVDS information.
Updated Figure 7–1 with BLVDS information and added Note 5.
Updated Table 7–1 and added BLVDS information.
Updated “Cyclone III High-Speed I/O Banks” section with BLVDS information.
Updated Table 7–2 and 7–6.
Added new section “BLVDS I/O Standard Support in Cyclone III Devices”.
Updated Note 4 to Figure 7–4.
Updated Note 1 to Figure 7–10.
Updated Note 1 to Figure 7–11.
Updated Note 1 to Figure 7–14.
Updated “Mini-LVDS I/O Standard Support in Cyclone III Devices” section.
Updated Note 1 to Figure 7–17.
Updated “LVPECL I/O Support in Cyclone III Devices” section.
Added new Figure 7–18.
Added note that PLL output clock pins do not support Class II type of
selected differential I/O standards.
Added Table 8–3 that lists the number of differential channels which are
migratable across densities and packages.
Updated (Note 4) to Figure 7–1.
Updated (Note 3) to Table 7–1.
Added new Table 7–3.
Added (Note 1) to Figure 7–21.
Added (Note 1) to Figure 7–23.
Added chapter TOC and “Referenced Documents” section.
Chapter 7: High-Speed Differential Interfaces in the Cyclone III Device Family
Changes Made
© December 2009 Altera Corporation
Chapter Revision History