EP1SGX10DF672C6N Altera, EP1SGX10DF672C6N Datasheet - Page 100
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10DF672C6N
Manufacturer Part Number
EP1SGX10DF672C6N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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TriMatrix Memory
Figure 4–19. EP1SGX40 Device with M-RAM Interface Locations
Note to
(1)
4–34
Stratix GX Device Handbook, Volume 1
Device shown is an EP1SGX40 device. The number and position of M-RAM blocks varies in other devices.
Figure
Blocks
DSP
4–19:
Blocks
top, bottom, and side opposite
M512
of block-to-block border.
M-RAM interface to
The M-RAM block local interconnect is driven by the R4, R8, C4, C8, and
direct link interconnects from adjacent LABs. For independent M-RAM
blocks, up to 10 direct link address and control signal input connections
to the M-RAM block are possible from the left adjacent LABs for M-RAM
M-RAM
M-RAM
Block
Block
LABs
Note (1)
interface to top, bottom, and side facing
device perimeter for easy access
M-RAM
M-RAM
Independent M-RAM blocks
Block
Block
to horizontal I/O pins.
Blocks
DSP
Altera Corporation
February 2005
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