EP1SGX10DF672C6N Altera, EP1SGX10DF672C6N Datasheet - Page 38
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10DF672C6N
Manufacturer Part Number
EP1SGX10DF672C6N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Figure 2–23. Data Path in Reverse Serial Loopback Mode
2–28
Stratix GX Device Handbook, Volume 1
Active Path
Non-Active Path
Deserializer
Recovery
Clock
Unit
Serializer
Aligner
Word
BIST (Built-In Self Test)
The Stratix GX transceiver has built-in self test modes to aid in debug and
testing. The BIST modes are set in the Stratix GX MegaWizard Plug-In
Manager in the Quartus II software. Only one BIST mode can be set for
any single instance of the transceiver block. The BIST mode applies to all
channels used in a transceiver.
The following is a list of the available BIST modes:
■
■
■
■
■
Figures 2–24
BIST incremental data path, respectively.
Channel
BIST PRBS
Aligner
Verifier
PRBS generator and verifier
Incremental mode generator and verifier
High-frequency generator
Low-frequency generator
Mixed-frequency generator
BIST PRBS
Generator
Encoder
8B/10B
and
Matcher
Rate
2–25
are diagrams of the BIST PRBS data path and the
Decoder
8B/10B
Serializer
Byte
Compensation
Deserializer
Phase
FIFO
Byte
Altera Corporation
Incremental
Verifier
Compensation
BIST
Phase
FIFO
June 2006
Generator
BIST
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