EP1SGX10DF672C6N Altera, EP1SGX10DF672C6N Datasheet - Page 184
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10DF672C6N
Manufacturer Part Number
EP1SGX10DF672C6N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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I/O Structure
4–118
Stratix GX Device Handbook, Volume 1
SSTL-3 class II
AGP (1
CTT
Table 4–28. I/O Support by Bank (Part 2 of 2)
×
I/O Standard
and 2
×
)
Each I/O bank has its own VCCIO pins. A single device can support 1.5-,
1.8-, 2.5-, and 3.3-V interfaces; each bank can support a different standard
independently. Each bank also has dedicated VREF pins to support any
one of the voltage-referenced standards (such as SSTL-3) independently.
Each I/O bank can support multiple standards with the same V
input and output pins. Each bank can support one voltage-referenced
I/O standard. For example, when V
LVTTL, LVCMOS, 3.3-V PCI, and SSTL-3 for inputs and outputs.
Differential On-Chip Termination
Stratix GX devices provide differential on-chip termination (LVDS I/O
standard) to reduce reflections and maintain signal integrity. Differential
on-chip termination simplifies board design by minimizing the number
of external termination resistors required. Termination can be placed
inside the package, eliminating small stubs that can still lead to
reflections. The internal termination is designed using transistors in the
linear region of operation.
Stratix GX devices support internal differential termination with a
nominal resistance value of 137.5 Ω for LVDS input receiver buffers.
LVPECL signals require an external termination resistor.
shows the device with differential termination.
Top & Bottom Banks
(3, 4, 7 & 8)
v
v
v
Left Banks
(1 & 2)
v
v
CCIO
is 3.3 V, a bank can support
Enhanced PLL External
Clock Output Banks
(9, 10, 11 & 12)
Altera Corporation
Figure 4–70
February 2005
v
v
v
CCIO
for
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