EP1SGX10DF672C6N Altera, EP1SGX10DF672C6N Datasheet - Page 136
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10DF672C6N
Manufacturer Part Number
EP1SGX10DF672C6N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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PLLs & Clock Networks
4–70
Stratix GX Device Handbook, Volume 1
Figure 4–41. Global Clock Resources
Regional Clock Network
There are four regional clock networks RCLK[3..0] within each
quadrant of the Stratix GX device that are driven by the same dedicated
CLK[7..0] and CLK[15..12] input pins, PLL outputs, or transceiver
clocks. The regional clock networks only pertain to the quadrant they
drive into. The regional clock networks provide the lowest clock delay
and skew for logic contained within a single quadrant. The CLK clock pins
symmetrically drive the RCLK networks within a particular quadrant, as
shown in
CLK[3..0]
Figure
4–42.
CLK[7..4]
Global Clock [15..0]
CLK[15..12]
Altera Corporation
February 2005
Transceiver
Clocks
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