EP1SGX10DF672C6N Altera, EP1SGX10DF672C6N Datasheet - Page 75
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10DF672C6N
Manufacturer Part Number
EP1SGX10DF672C6N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Altera Corporation
February 2005
for accumulator functions. Another portion of the LUT generates carry-
out bits. An LAB-wide carry in bit selects which chain to use for the
addition of given inputs. The carry-in signal for each chain, carry-in0
or carry-in1, selects the carry-out to carry forward to the carry-in
signal of the next-higher-order bit. The final carry-out signal is routed to
an LE, where it is fed to local, row, or column interconnects.
The Quartus II Compiler automatically creates carry chain logic during
design processing, or you can create it manually during design entry.
Parameterized functions such as LPM functions automatically take
advantage of carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 10 LEs by
linking LABs together automatically. For enhanced fitting, a long carry
chain runs vertically allowing fast horizontal connections to TriMatrix
memory and DSP blocks. A carry chain can continue as far as a full
column.
Stratix GX Device Handbook, Volume 1
Stratix GX Architecture
4–9
™
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