EP1SGX10DF672C6N Altera, EP1SGX10DF672C6N Datasheet - Page 43
![IC STRATIX GX FPGA 10KLE 672FBGA](/photos/6/72/67292/544-672-fbga_sml.jpg)
EP1SGX10DF672C6N
Manufacturer Part Number
EP1SGX10DF672C6N
Description
IC STRATIX GX FPGA 10KLE 672FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX10DF672C6N
Number Of Logic Elements/cells
10570
Number Of Labs/clbs
1057
Total Ram Bits
920448
Number Of I /o
362
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Altera Corporation
June 2006
The receiver PLL can also drive the fast regional, regional clocks, and
local routing adjacent to the associated transceiver block.
through
used by the recovered clock.
In the EP1SGX25 device, the receiver PLL recovered clocks from
transceiver blocks 0 and 1 drive RCLK[1..0] while transceiver blocks 2
and 3 drive RCLK[7..6]. The regional clocks feed logic in their
associated regions.
Figure 2–28. EP1SGX25 Receiver PLL Recovered Clock to Regional Clock
Connection
In addition, the receiver PLL’s recovered clocks can drive fast regional
lines (FCLK) as shown
in their associated regions.
2–31
show which fast regional and regional clock resource can be
Figure
2–29. The fast regional clocks can feed logic
PLD
Stratix GX Device Handbook, Volume 1
RCLK[11..10]
RCLK[9..8]
Transceiver Blocks
Stratix GX Transceivers
Stratix GX
Block 0
Block 1
Block 2
Block 3
Figures 2–28
2–33
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