EP1SGX25DF672I6 Altera, EP1SGX25DF672I6 Datasheet - Page 133

• Manufacturer Part Number: EP1SGX25DF672I6
• Description: IC STRATIX GX FPGA 25K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25DF672I6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Figure 4–40. DSP Block Interface to Interconnect
Altera Corporation
February 2005
C4 and C8
Interconnects
LAB
DSP Block to
LAB Row Interface
Block Interconnect Region
Direct Link Interconnect
from Adjacent LAB
10
A bus of 18 control signals feeds the entire DSP block. These signals
include clock[0..3] clocks, aclr[0..3] asynchronous clears,
ena[1..4] clock enables, signa, signb signed/unsigned control
signals, addnsub1 and addnsub3 addition and subtraction control
signals, and accum_sload[0..1] accumulator synchronous loads. The
Row Interface
18
3
Block
18 Inputs per Row
R4 and R8 Interconnects
10
9
Control
[17..0]
DSP Block
Row Structure
Stratix GX Device Handbook, Volume 1
[17..0]
18 Outputs per Row
Nine Direct Link Outputs
to Adjacent LABs
18
18
9
Stratix GX Architecture
Direct Link Interconnect
from Adjacent LAB
LAB
4–67