EP1SGX25DF672I6 Altera, EP1SGX25DF672I6 Datasheet - Page 5

• Manufacturer Part Number: EP1SGX25DF672I6
• Description: IC STRATIX GX FPGA 25K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25DF672I6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Altera Corporation
February 2005
Note to
(1)
LEs
Transceiver channels
Source-synchronous channels
M512 RAM blocks (32
M4K RAM blocks (128
M-RAM blocks (4K
Total RAM bits
Digital signal processing (DSP) blocks
Embedded multipliers
PLLs
Table 1–1. Stratix GX Device Features
This parameter lists the total number of 9- × 9-bit multipliers for each device. For the total number of 18- × 18-bit
multipliers per device, divide the total number of 9- × 9-bit multipliers by 2. For the total number of 36- × 36-bit
multipliers per device, decide the total number of 9- × 9-bit multipliers by 8.
Table
1–1:
×
Feature
144 bits)
(1)
×
×
18 bits)
36 bits)
Stratix GX devices are available in space-saving FineLine BGA
(refer to
Table
package (that is, you can migrate between the EP1SGX10C and
EP1SGX25C devices in the 672-pin FineLine BGA package). See the
Stratix GX device pin tables for more information. Vertical migration
means that you can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package
across device densities. For I/O pin migration across densities, you must
cross-reference the available I/O pins using the device pin-outs for all
planned densities of a given package type, to identify which I/O pins it
is possible to migrate. The Quartus II software can automatically cross
reference and place all pins for migration when given a device migration
list.
EP1SGX10C
EP1SGX10D
EP1SGX25C
Table 1–2. Stratix GX Package Options & I/O Pin Counts (Part 1
of 2)
1–4). Stratix GX devices support vertical migration within the same
Device
Tables 1–2
Note (1)
and 1–3), and in multiple speed grades (refer to
EP1SGX10C
EP1SGX10D
920,448
10,570
672-Pin FineLine BGA
4, 8
22
94
60
48
Introduction to the Stratix GX Device Data Sheet
1
6
4
362
362
455
Stratix GX Device Handbook, Volume 1
EP1SGX25D
EP1SGX25C
EP1SGX25F
1,944,576
4, 8, 16
25,660
224
138
39
10
80
2
4
1,020-Pin FineLine BGA
EP1SGX40D
EP1SGX40G
3,423,744
41,250
8, 20
®
384
183
112
45
14
4
8
packages
1–3