EP1SGX25DF672I6 Altera, EP1SGX25DF672I6 Datasheet - Page 56

• Manufacturer Part Number: EP1SGX25DF672I6
• Description: IC STRATIX GX FPGA 25K 672-FBGA
• Manufacturer: Altera
• Series: Stratix® GXr

Specifications of EP1SGX25DF672I6

• Number Of Logic Elements/cells: 25660
• Number Of Labs/clbs: 2566
• Total Ram Bits: 1944576
• Number Of I /o: 455
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 672-FBGA
• Family Name: Stratix GX
• Number Of Logic Blocks/elements: 25660
• # I/os (max): 455
• Frequency (max): 5GHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 25660
• Ram Bits: 1944576
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 672
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant

Introduction
3–6
Stratix GX Device Handbook, Volume 1
Unlike the de-skew function in APEX
you do not have to use a fixed training pattern with DPA in Stratix GX
devices.
circuitry with DPA and source-synchronous circuitry without DPA
circuitry in Stratix GX devices.
DPA Input Support
Stratix GX device I/O banks 1 and 2 contain dedicated circuitry to
support differential I/O standards at speeds up to 1 Gbps with DPA (or
up to 840 Mbps without DPA). Stratix GX device source-synchronous
circuitry supports LVDS, LVPECL, and 3.3-V PCML I/O standards, each
with a supply voltage of 3.3 V. Refer to the High-Speed Source-Synchronous
Differential I/O Interfaces in Stratix GX Devices chapter of the Stratix GX
Device Handbook, Volume 2 for more information on these I/O standards.
Transmitter pins can be either input or output pins for single-ended I/O
standards. Refer to
Interface & Fast PLL
This section describes the number of channels that support DPA and their
relationship with the PLL in Stratix GX devices. EP1SGX10 and
EP1SGX25 devices have two dedicated fast PLLs and EP1SGX40 devices
Data rate
Deserialization factors
Clock frequency
Interface pins
Receiver pins
Differential
Single ended
Table 3–1. Source-Synchronous Circuitry With & Without DPA
Table 3–2. Bank 1 & 2 Input Pins
Input Pin Type
Table 3–1
Feature
shows the differences between source-synchronous
Differential
Single ended
Table
I/O Standard
3–2.
300 to 840 Megabits per
second (Mbps)
1, 2, 4, 8, 10
10 to 717 MHz
I/O banks 1 and 2
Dedicated inputs
Without DPA
Source-Synchronous Circuitry
Input only
Input only
TM
Receiver Pin
20KE and APEX 20KC devices,
300 Mbps to 1 Gbps
8, 10
74 to 717 MHz
I/O banks 1 and 2
Dedicated inputs
Altera Corporation
Output only
Input or output
With DPA
Transmitter Pin
August 2005