XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 215
![IC FPGA VIRTEX-5 ES 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX30T-1FFG665CES
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Quantity:
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Multiplexer Primitives
Carry Chain Primitive
Port Signals
X-Ref Target - Figure 5-35
Two primitives (MUXF7 and MUXF8) are available for access to the dedicated F7AMUX,
F7BMUX and F8MUX in each slice. Combined with LUTs, these multiplexer primitives are
also used to build larger width multiplexers (from 8:1 to 16:1). The
Multiplexers
Data In – I0, I1
The data input provides the data to be selected by the select signal (S).
Control In – S
The select input signal determines the data input signal to be connected to the output O.
Logic 0 selects the I0 input, while logic 1 selects the I1 input.
Data Out – O
The data output O provides the data value (one bit) selected by the control inputs.
The CARRY4 primitive represents the fast carry logic for a slice in the Virtex-5 architecture.
This primitive works in conjunction with LUTs in order to build adders and multipliers.
This primitive is generally inferred by synthesis tools from standard RTL code. The
synthesis tool can identify the arithmetic and/or logic functionality that best maps to this
00111
D
5
D
D
D
A[4:0]
SRLC32G
SRLC32G
SRLC32G
section provides more information on building larger multiplexers.
LUT
LUT
LUT
Figure 5-35: Example Static-Length Shift Register
Q31
Q31
Q31
Q
www.xilinx.com
OUT
(72-bit SRL)
00110
D
5
D
SRLC32G
D
SRLC32G
D
A[4:0]
SRLC32G
LUT
LUT
LUT
Q31
Q31
Q31
Q
D
Designing Large
FF
Q
CLB Primitives
UG190_5_35_050506
OUT
(72-bit SRL)
215
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