XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 40
![IC FPGA VIRTEX-5 ES 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX30T-1FFG665CES
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Chapter 1: Clock Resources
Regional Clocking Resources
40
Clock Capable I/O
Regional clock networks are a set of clock networks independent of the global clock
network. Unlike global clocks, the span of a regional clock signal (BUFR) is limited to three
clock regions, while the I/O clock signal drives a single region only. These networks are
especially useful for source-synchronous interface designs. The I/O banks in Virtex-5
devices are the same size as a clock region.
To understand how regional clocking works, it is important to understand the signal path
of a regional clock signal. The regional clocking resources and network in Virtex-5 devices
consist of the following paths and components:
•
•
•
•
In a typical clock region there are four clock-capable I/O pin pairs (there are exceptions in
the center column). Clock-capable I/O pairs are regular I/O pairs in select locations with
special hardware connections to nearby regional clock resources. Some global clock inputs
are also clock-capable I/Os. There are four dedicated clock-capable I/O sites in every
bank. When used as clock inputs, clock-capable pins can drive BUFIO and BUFR. Clock-
capable I/Os in the center column can not drive BUFRs. Clock-capable I/Os can not
directly connect to the global clock buffers. When used as single-ended clock pins, then as
described in
connection only exists on this pin.
Clock Capable I/O
I/O Clock Buffer - BUFIO
Regional Clock Buffer - BUFR
Regional Clock Nets
Global Clock
www.xilinx.com
Buffers, the P-side of the pin pair must be used because a direct
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
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