XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 92
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XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX30T-1FFG665CES
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Xilinx Inc
Quantity:
10 000
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Chapter 3: Phase-Locked Loops (PLLs)
General Usage Description
92
PLL Primitives
PLL_BASE Primitive
Figure 3-4
X-Ref Target - Figure 3-4
The PLL_BASE primitive provides access to the most frequently used features of a stand
alone PLL. Clock deskew, frequency synthesis, coarse phase shifting, and duty cycle
programming are available to use with the PLL_BASE. The ports are listed in
Table 3-1: PLL_BASE Ports
Clock Input
Control Inputs
Clock Output
Status and Data Outputs
Description
CLKIN1
CLKFBIN
RST
shows the two Virtex-5 FPGA PLL primitives, PLL_BASE and PLL_ADV.
PLL_BASE
CLKFBOUT
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
LOCKED
www.xilinx.com
CLKIN, CLKFBIN
RST
CLKOUT0 to CLKOUT5, CLKFBOUT
LOCKED
Figure 3-4: PLL Primitives
Port
CLKIN1
CLKIN2
CLKFBIN
RST
CLKINSEL
DADDR[4:0]
DI[15:0]
DWE
DEN
DCLK
REL
PLL_ADV
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
CLKOUTDCM0
CLKOUTDCM1
CLKOUTDCM2
CLKOUTDCM3
CLKOUTDCM4
CLKOUTDCM5
CLKFBDCM
CLKFBOUT
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
LOCKED
DO[15:0]
UG190_c3_04_022709
DRDY
Table
3-1.
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