XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 7
![IC FPGA VIRTEX-5 ES 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5VLX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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UG190 (v5.3) May 17, 2010
05/01/09
06/19/09
09/18/09
05/17/10
11/05/09
Date
Version
4.7
5.0
5.1
5.2
5.3
Chapter 3: Added 7 as one of the values of D in the last sentence of the first paragraph of
Determine the Input Frequency, page
Chapter 4: In the second paragraph of
paragraph. Changed “Clock Cycle Latency” to “Write/Read Cycle Latency” in
Table 4-16, page
NO_CHANGE in the last bullet of the section.
Chapter 1: Updated instances of BUFGMUX_VIRTEX4 to BUFGMUX_CTRL throughout
chapter. Clarified global and local clocking in first paragraph of
Clocks, page
Chapter 2: Updated Dynamic Reconfiguration description in
remove “different phase shift” as an attribute changeable via dynamic reconfiguration.
Chapter 3: Updated definition of LOCKED pin in
Chapter 5: Changed “combine all slices” to “combine all LUTs” in second paragraph of
Look-Up Table (LUT), page
Read Operation, page
Chapter 6: In
• Sentence that stated that DCI control for a particular bank can come from the bank
• Fourth bulleted item in guidelines when using DCI cascading that stated that DCI
Chapter 2: In first paragraph of
powering down when CLKIN is stopped for 100 ms or longer.
immediately above or below.
cascading must extend across consecutive banks in the same column.
25.
DCI Cascading, page
145. In
www.xilinx.com
195.
ECC Modes Overview, page
178. Changed “16” to “32” in the first paragraph of
Source Clock Input -
220, deleted the following:
95. Updated waveform 1 in
Write Modes, page
Revision
Table 3-3, page
CLKIN, added sentence about DCM
159, changed READ_FIRST to
117, rephrased the second
DCM Summary, page 48
Virtex-5 FPGA User Guide
Global and Regional
96.
Figure 3-10, page
Static
105.
to
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