XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 340
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XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Part Number:
XC5VLX30T-1FFG665CES
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Chapter 7: SelectIO Logic Resources
X-Ref Target - Figure 7-17
340
1 Clock Region
IDELAYCTRL
IDELAYCTRL Usage and Design Guidelines
This section describes using the IDELAYCTRL modules, design guidelines, and
recommended usage in Virtex-5 devices.
Instantiating IDELAYCTRL Without LOC Constraints
When instantiating IDELAYCTRL without LOC constraints, the user must instantiate only
one instance of IDELAYCTRL in the HDL design code. The implementation tools auto-
replicate IDELAYCTRL instances throughout the entire device. When IDELAYCTRL
instances are replicated to clock regions but not used, the extra instances are trimmed out
of the design automatically by the ISE software. The signals connected to the RST and
REFCLK input ports of the instantiated IDELAYCTRL instance are connected to the
corresponding input ports of the replicated IDELAYCTRL instances.
There are two special cases:
1.
Figure 7-17: Relative Locations of IDELAYCTRL Modules
When the RDY port is ignored, the RDY signals of all the replacement IDELAYCTRL
instances are left unconnected.
The VHDL and Verilog use models for instantiating an IDELAYCTRL primitive
without LOC constraints leaving the RDY output port unconnected are provided in
the Libraries Guide.
The resulting circuitry after instantiating the IDELAYCTRL components is illustrated
in
Column
Left I/O
Figure
7-18.
www.xilinx.com
Center I/O
Column
CMT
CMT
Configuration
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Right I/O
Column
ug190_7_12_041206
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