XC5VLX30T-1FFG665CES Xilinx Inc, XC5VLX30T-1FFG665CES Datasheet - Page 286
![IC FPGA VIRTEX-5 ES 30K 665FCBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VLX30T-1FFG665CES
Manufacturer Part Number
XC5VLX30T-1FFG665CES
Description
IC FPGA VIRTEX-5 ES 30K 665FCBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 LXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VLX30T-1FFG665CES
Number Of Logic Elements/cells
30720
Number Of Labs/clbs
2400
Total Ram Bits
1327104
Number Of I /o
360
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
665-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Available stocks
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Part Number
Manufacturer
Quantity
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Company:
Part Number:
XC5VLX30T-1FFG665CES
Manufacturer:
Xilinx Inc
Quantity:
10 000
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Chapter 6: SelectIO Resources
286
Differential SSTL Class I (1.8V)
Figure 6-78
differential SSTL Class I (1.8V) with unidirectional termination.
X-Ref Target - Figure 6-78
Figure 6-79
differential SSTL Class I (1.8V) with unidirectional DCI termination.
X-Ref Target - Figure 6-79
DIFF_SSTL18_I_DCI
DIFF_SSTL18_I_DCI
Figure 6-79: Differential SSTL (1.8V) Class I Unidirectional DCI Termination
External Termination
DIFF_SSTL18_I
DIFF_SSTL18_I
Figure 6-78: Differential SSTL (1.8V) Class I Unidirectional Termination
DCI
R 0 = 20
R 0 = 20
shows a sample circuit illustrating a valid termination technique for
shows a sample circuit illustrating a valid termination technique for
Ω
Ω
IOB
IOB
www.xilinx.com
R S = 20Ω
R S = 20Ω
Z 0
Z 0
R P = Z 0 = 50Ω
Z 0
Z 0
IOB
V
V
CCO
CCO
2R
2R
2R
2R
= 1.8V
= 1.8V
V
V
TT
TT
VRP
VRN
VRP
VRN
= 0.9V
= 0.9V
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
= 2Z 0 = 100Ω
50Ω
IOB
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
DIFF_SSTL18_I_DCI
+
–
DIFF_SSTL18_I
ug190_6_73_030506
+
–
ug190_6_74_032206
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