ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 6

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
MEMORY ARCHITECTURE
The ADSP-BF54x processors view memory as a single unified
4G byte address space, using 32-bit addresses. All resources,
including internal memory, external memory, and I/O control
registers, occupy separate sections of this common address
space. The memory portions of this address space are arranged
in a hierarchical structure to provide a good cost/performance
balance of some very fast, low-latency on-chip memory as cache
or SRAM, and larger, lower-cost and performance off-chip
memory systems. See
The on-chip L1 memory system is the highest-performance
memory available to the Blackfin processor. The off-chip mem-
ory system, accessed through the external bus interface unit
(EBIU), provides expansion with flash memory, SRAM, and
double-rate SDRAM (standard or mobile DDR), optionally
accessing up to 768M bytes of physical memory.
Most of the ADSP-BF54x Blackfin processors also include an L2
SRAM memory array which provides up to 128K bytes of high
speed SRAM, operating at one half the frequency of the core and
with slightly longer latency than the L1 memory banks (for
information on L2 memory in each processor, see
L2 memory is a unified instruction and data memory and can
hold any mixture of code and data required by the system
design. The Blackfin cores share a dedicated low latency 64-bit
data path port into the L2 SRAM memory.
The memory DMA controllers (DMAC1 and DMAC0) provide
high-bandwidth data-movement capability. They can perform
block transfers of code or data between the internal memory
and the external memory spaces.
Internal (On-Chip) Memory
The ADSP-BF54x processors have several blocks of on-chip
memory providing high bandwidth access to the core.
The first block is the L1 instruction memory, consisting of
64K bytes of SRAM, of which 16K bytes can be configured as a
four-way set-associative cache or as SRAM. This memory is
accessed at full processor speed.
The second on-chip memory block is the L1 data memory, con-
sisting of 64K bytes of SRAM, of which 32K bytes can be
configured as a two-way set-associative cache or as SRAM. This
memory block is accessed at full processor speed.
The third memory block is a 4K byte scratchpad SRAM, which
runs at the same speed as the L1 memories. It is only accessible
as data SRAM and cannot be configured as cache memory.
The fourth memory block is the factory programmed L1
instruction ROM, operating at full processor speed. This ROM
is not customer-configurable.
The fifth memory block is the L2 SRAM, providing up to 128K
bytes of unified instruction and data memory, operating at one
half the frequency of the core.
Finally, there is a 4K byte boot ROM connected as L3 memory.
It operates at full SCLK rate.
Figure 3 on Page
6.
Table
Rev. C | Page 6 of 100 | February 2010
1). The
1
External (Off-Chip) Memory
Through the external bus interface unit (EBIU), the
ADSP-BF54x Blackfin processors provide glueless connectivity
to external 16-bit wide memories, such as DDR and mobile
DDR SDRAM, SRAM, NOR flash, NAND flash, and FIFO
devices. To provide the best performance, the bus system of the
DDR and mobile DDR interface is completely separate from the
other parallel interfaces. Furthermore, the DDR controller sup-
ports either standard DDR memory or mobile DDR memory.
See the
this document, references to “DDR” are intended to cover both
the standard and mobile DDR standards.
For ADSP-BF544 processors, L2 SRAM is 64K Bytes (0xFEB0000–0xFEB0FFFF).
For ADSP-BF542 processors, there is no L2 SRAM.
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
TOP OF LAST
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
0x
FFFF FFFF
DDR PAGE
FFE0 0000
FFC0 0000
FFB0 1000
FFB0 0000
FFA2 4000
FFA1 4000
FFA1 0000
FFA0 8000
FFA0 0000
FEB2 0000
FEB0 0000
FFA0
FF90 8000
FF90 4000
FF90 0000
FF80 8000
FF80 4000
FF80 0000
EF00 1000
EF00 0000
2C00 0000
3000 0000
2800 0000
2400 0000
2000 0000
0000 0000
Ordering Guide on Page 100
C000
Figure 3. ADSP-BF547/ADSP-BF548/ADSP-BF549
CORE MMR REGISTERS (2M BYTES)
SYSTEM MMR REGISTERS (2M BYTES)
RESERVED
SCRATCHPAD SRAM (4K BYTES)
RESERVED
L1 ROM (64K BYTE)
INSTRUCTION SRAM / CACHE (16K BYTES)
RESERVED
INSTRUCTION BANK B SRA M (16K BYTES)
INSTRUCTION BANK A SRA M (32K BYTES)
RESERVED
DATA BANK B SRAM / CACHE (16K BYTES)
DATA BANK B SRAM (16 K BYTES)
RESERVED
DATA BANK A SRAM / CACHE (16K BYTES)
DATA BANK A SRAM (16 K BYTES)
L2 SRAM (128K BYTES)
RESERVED
B OOT ROM (4K BYTES)
RESERVED
ASYNC MEMORY BANK 3 (64M BYTES)
ASYNC MEMORY BANK 2 (64M BYTES)
ASYNC MEMORY BANK 1 (64M BYTES)
ASYNC MEMORY BANK 0 (64M BYTES)
RESERVED
DDR MEM BANK 1 (8M BYTES to 256M BYTES)
DDR MEM BANK 0 (8M BYTES to 256M BYTES)
Internal/External Memory Map
RESERVED
for details. Throughout
1