ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 75

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Register and PIO
Table 58
data transfer timing.
Table 58. ATAPI Register and PIO Data Transfer Timing
1
Figure 47
that ATAPI_ADDR pins include A1-3, ATAPI_CS0, and
ATAPI_CS1. Alternate ATAPI port ATAPI _ADDR pins
1
ATAPI Parameter/Description
t
t
t
t
t
t
t
t
t
t
ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for the ATA device mode of
This material is adapted from ATAPI-6 (INCITS 361-2002[R2007] and is used with permission of the American National Standards Institute (ANSI) on behalf of the
0
1
2
2i
3
4
5
6
9
A
operation.
Information Technology Industry Council (“ITIC”). Copies of ATAPI-6 (INCITS 361-2002[R2007] can be purchased from ANSI.
and
displays the REG and PIO data transfer timing. Note
Cycle time
ATAPI_ADDR valid to
ATAPI_DIOR/ATAPI_DIOW setup
ATAPI_DIOR/ATAPI_DIOW pulse width
ATAPI_DIOR/ATAPI_DIOW recovery time
ATAPI_DIOW data setup
ATAPI_DIOW data hold
ATAPI_DIOR data setup
ATAPI_DIOR data hold
ATAPI_DIOR/ATAPI_DIOW to ATAPI_ADDR
valid hold
ATAPI_IORDY setup time
Figure 47
ATAPI_IORDY
ATAPI_IORDY
ATAPI_D0–15
ATAPI_D0–15
ATAPI_DIOR/
ATAPI_DIOW
(WRITE)
(READ)
ATAPI
ADDR
describe the ATAPI register and the PIO
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
t
1
Figure 47. REG and PIO Data Transfer Timing
Rev. C | Page 75 of 100 | February 2010
ATAPI_REG/PIO_TIM_x Timing Register
Setting
T2_PIO, TEOC_PIO
T1
T2_PIO
TEOC_PIO
T2_PIO
T4
N/A
N/A
TEOC_PIO
T2_PIO
t
A
1
t
2
include ATAPI_A0A, ATAPI_A1A, ATAPI_A2A, ATAPI_CS0,
and ATAPI_CS1. Note that an alternate ATAPI_D0-15 port bus
is ATAPI_D0-15A
t
3
t
t
0
5
1
Timing Equation
(T2_PIO + TEOC_PIO) × t
T1 × t
T2_PIO × t
TEOC_PIO × t
T2_PIO × t
T4 × t
t
0
TEOC_PIO × t
T2_PIO × t
OD
+ t
t
SCLK
SCLK
9
SUD
– (t
– (t
+ 2 × t
SCLK
SCLK
SCLK
t
2i
SK1
SK1
SCLK
SCLK
– (t
– (t
+ t
+ t
BD
OD
– (t
SK1
SK2
SK2
+ t
+ t
+ t
SK1
CDD
+ t
+ t
SUI
SK2
+ t
SK4
SK4
+ t
+ 2 × t
SCLK
+ t
SK2
)
)
CDC
SK4
+ t
CDC
)
SK4
+ 2 × t
)
BD
)