ADSP-3PARCBF548M01 Analog Devices Inc, ADSP-3PARCBF548M01 Datasheet - Page 76

• Manufacturer Part Number: ADSP-3PARCBF548M01
• Description: MODULE BOARD BF548
• Manufacturer: Analog Devices Inc
• Series: Blackfin®r

Specifications of ADSP-3PARCBF548M01

• Module/board Type: Processor Module
• For Use With/related Products: ADSP-BF548
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
ATAPI Multiword DMA Transfer Timing
Table 59
multiword DMA transfer timing.
Table 59. ATAPI Multiword DMA Transfer Timing
1
ATAPI Parameter/Description
t
t
t
t
t
t
t
t
t
t
t
t
t
ATAPI timing register setting should be programmed with a value that guarantees parameter compliance with the ATA ANSI specification for an ATA device mode of
0
D
F
G(write)
G(read)
H
I
J
KR
KW
LR
M
N
operation.
and
Cycle time
ATAPI_DIOR/ATAPI_DIOW asserted
Pulse Width
ATAPI_DIOR data hold
ATAPI_DIOW data setup
ATAPI_DIOR data setup
ATAPI_DIOW data hold
ATAPI_DMACK to
ATAPI_DIOR/ATAPI_DIOW setup
ATAPI_DIOR/ATAPI_DIOW to
ATAPI_DMACK hold
ATAPI_DIOR negated pulse width
ATAPI_DIOW negated pulse width
ATAPI_DIOR to ATAPI_DMARQ delay N/A
ATAPI_CS0-1 valid to
ATAPI_DIOR/ATAPI_DIOW
ATAPI_CS0-1 hold
Figure 48
through
Figure 51
describe the ATAPI
ATAPI_MULTI_TIM_x Timing Register
Setting
TD, TK
TD
N/A
TD
TD
TK
TM
TK, TEOC_MDMA
TKR
TKW
TM
TK, TEOC_MDMA
Rev. C | Page 76 of 100 | February 2010
1
Timing Equation
(TD + TK) × t
TD × t
0
TD × t
t
TK × t
TM × t
(TK + TEOC_MDMA) × t
TKR × t
TKW × t
(TD + TK) × t
TM × t
(TK + TEOC_MDMA) × t
OD
+ t
SCLK
SCLK
SCLK
SUD
SCLK
SCLK
SCLK
SCLK
+ 2 × t
– (t
– (t
– (t
– (t
SCLK
SK1
SCLK
SK1
SK1
SK1
+ t
+ t
BD
+ t
+ t
– (t
+ t
SK2
SK2
SK2
SK2
OD
CDD
+ t
+ t
+ t
+ t
+ 2 × t
SCLK
SCLK
SK4
SK4
+ t
SK4
SK4
)
)
)
)
CDC
– (t
– (t
BD
SK1
SK1
+ 2 × t
+ t
+ t
SK2
SK2
CDC
+ t
+ t
)
SK4
SK4
)
)