CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet
CY7C63413C-PVXC
Specifications of CY7C63413C-PVXC
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CY7C63413C-PVXC Summary of contents
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... CMOS outputs. The CY7C63413C/513C have 24 GPIO pins (Ports that are rated typical sink current. The CY7C63413C/513C has 8 GPIO pins (Port 3) that are rated typical sink current, which allows these pins to drive LEDs. The CY7C63613C features 16 GPIO pins to support USB and other applications ...
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... This clock generator reduces the clock-related noise emissions (EMI). The clock generator provides the 6 and 12-MHz clocks that remain internal to the microcontroller. The CY7C63413C/513C/613C are offered with single EPROM options. The CY7C63413C, CY7C63513C and the CY7C63613C have 8 Kbytes of EPROM. These parts include Power-on Reset logic, a Watch Dog Timer, a vectored interrupt controller, and a 12-bit free-running timer ...
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... Truth Tables .................................................................... 23 Absolute Maximum Ratings .......................................... 27 DC Characteristics ......................................................... 27 Switching Characteristics .............................................. 28 Ordering Information ...................................................... 31 Ordering Code Definition ........................................... 31 Die Pad Locations .......................................................... 32 Package Diagrams .......................................................... 33 Acronyms ........................................................................ 35 Document Conventions ................................................. 35 Units of Measure. ...................................................... 35 Sales, Solutions, and Legal Information ...................... 36 Worldwide Sales and Design Support ....................... 36 Products .................................................................... 36 PSoC Solutions ......................................................... 36 CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... Vss 24 25 XTAL XTAL IN IN CY7C63613C 24-pin SOIC D– P3[ P3[6] P3[ P3[4] P1[ P1[2] P1[ P1[0] P0[ P0[6] P0[ P0[4] P0[ P0[2] P0[ P0[ XTAL PP OUT Vss 12 13 XTAL IN CY7C63413C 48-Pad Die P3[2] P3[0] P2[6] P2[4] P2[2] P2[0] P1[6] P1[4] P1[2] P1[0] DAC[6] DAC[4] P0[6] P0[4] Page [+] Feedback ...
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... Programming Model 14-bit Program Counter (PC) The 14-bit Program Counter (PC) allows access for kilobytes of EPROM using the CY7C63413C/513C/613C architecture. The program counter is cleared during reset, such that the first instruction executed after a reset is at address 0x0000. This is typically a jump instruction to a reset handler that initializes the application ...
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... For USB applications strongly recommended that the DSP is loaded after reset just below the USB DMA buffers. Address Modes The CY7C63413C/513C/613C microcontrollers support three addressing modes for instructions that require data operands: data, direct, and indexed. Document #: 38-08027 Rev. *E Data The “ ...
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... AND [expr],A 5 AND [X+expr],A 7 XOR [expr],A 8 XOR [X+expr],A 4 IOWX [X+expr] 5 CPL 6 ASL 4 ASR 5 RLC RRC 4 RET RETI JNC 5 JACC 5 INDEX CY7C63413C CY7C63513C CY7C63613C operand opcode cycles 20 4 acc direct 23 7 index 24 8 acc direct 27 7 index 28 8 address 29 5 ...
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... USB address A endpoint 2 interrupt vector 0x000E Reserved 0x0010 Reserved 0x0012 Reserved 0x0014 DAC interrupt vector 0x0016 GPIO interrupt vector 0x0018 Reserved 0x001A Program Memory begins here ( bytes) 0x1FDF 8-KB PROM ends here (CY7C63413C, CY7C63513C, CY7C63613C) CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... Data Memory Organization The CY7C63413C/513C/613C microcontrollers provide 256 bytes of data RAM. In normal usage, the SRAM is partitioned into four areas: program stack, data stack, user variables and USB endpoint FIFOs as shown below: after reset Address 8-bit PSP 0x00 8-bit DSP user 0xE8 ...
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... W Watch Dog Reset clear [2] R/W DAC I/O W Interrupt enable for each DAC pin W Interrupt polarity for each DAC pin W One four bit sink current register for each DAC pin R/W Microprocessor status and control CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... Watch Dog Reset because the USB Device Address Register is cleared. Otherwise, the USB Controller would respond to all address 0 transactions. The USB transmitter remains disabled until the MSB of the USB address register is set. voltage to the CC CY7C63413C CY7C63513C CY7C63613C XTALOUT XTALIN ) and the USB I/O are at the CC ...
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... Latch 7 k Port Write Q2 Internal Buffer Port Read to Interrupt Controller Port 0 Data P0[4] P0[3] R/W R/W Port 1 Data P1[4] P1[3] R/W R/W CY7C63413C CY7C63513C CY7C63613C Q3 GPIO Pin ESD P0[2] P0[1] P0[0] R/W R/W R/W P1[2] P1[1] P1[0] R/W R/W R/W ...
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... As shown in the table below, when a GPIO port is configured with CMOS outputs, interrupts from that port are disabled. The GPIO Configuration Port register provides two bits per port to program these fea- tures. The possible port configurations are as shown in CY7C63413C CY7C63513C CY7C63613C P2[1] P2[0] ...
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... During reset, all of the bits in the GPIO Configuration Register are written with “0.” This selects the default configuration: Open Drain output, positive interrupt polarity for all GPIO ports. GPIO Configuration Register Port 2 Port 1 Port 1 Config Bit 0 Config Bit 1 Config Bit CY7C63413C CY7C63513C CY7C63613C P0[1] P0[ P1[1] P1[ P2[1] P2[ P3[1] ...
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... LOW. The first Isink register (0x38) controls the current for DAC[0], the second (0x39) for DAC[1], and so on until the Isink register at 0x3F controls the current to DAC[7]. CY7C63413C CY7C63513C CY7C63613C DAC I/O Pin ...
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... Table 16. DAC Port Isink Addr: 0x38-0x3F Reserved Document #: 38-08027 Rev. *E DAC Port Interrupt Enable DAC[4] DAC[3] DAC[ DAC Port Interrupt Polarity DAC[4] DAC[3] DAC[ DAC Port Interrupt Polarity Isink[3] Isink[ CY7C63413C CY7C63513C CY7C63613C DAC[1] DAC[ DAC[1] DAC[ Isink Value Isink[1] Isink[ Page [+] Feedback ...
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... USB Controller retrieves the descriptors from its program space and returns the data to the host over the USB. PS/2 Operation PS/2 operation is possible with the CY7C63413C/513C/613C series through the use of firmware and several operating modes. The first enabling feature: 1. USB Bus reset on D+ and D interrupt that can be dis- abled ...
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... Address Bit 4 Bit 3 R/W R/W USB Device EPA0, Mode Register Acknowledge Mode Bit 3 R/W R/W USB Device Endpoint Mode Register Acknowledge Mode Bit 3 R/W R/W CY7C63413C CY7C63513C CY7C63613C Figure 18 shows the Table 19. Table 20. Device Device Address Address Bit 2 Bit 1 Bit 0 R/W ...
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... OUT and set-up tokens only. Data 0/1 Toggle bit 7 selects the DATA packet’s toggle state: 0 for DATA0, 1 for DATA1. USB Device Counter Registers Reserved Byte count Byte count Bit 3 Bit 2 R/W R/W R/W CY7C63413C CY7C63513C CY7C63613C Byte count Byte count Bit 1 Bit 0 R/W R/W Page [+] Feedback ...
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... Timer Register (LSB) Timer Timer Bit 4 Bit Timer Register (MSB) Reserved Timer Bit 11 R Figure 6. Timer Block Diagram CY7C63413C CY7C63513C CY7C63613C Timer Timer Timer Bit 2 Bit 1 Bit Timer Timer Timer Bit 10 Bit 9 Bit 1.024-ms interrupt 128- s interrupt 0 1-MHz clock D0 ...
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... POP A instruction should be used just before the RETI instruction to restore the accumulator value. The program counter CF and ZF are restored and interrupts are enabled when the RETI instruction is executed. CY7C63413C CY7C63513C CY7C63613C POR Default: 0x0101 WDC Reset: 0x41 ...
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... Please note that if one DAC pin triggered an interrupt, no other DAC pins can cause a DAC interrupt until that pin has returned to its inactive (non-trigger) state or the corresponding interrupt enable bit is cleared. The USB Controller does not assign CY7C63413C CY7C63513C CY7C63613C 2 1 ...
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... Out), but must be placed in the correct mode to function as such. Also a non-Control endpoint can be made to act as a Control endpoint placed in a non appropriate mode. A ‘check’ Out token during a Status transaction checks to see that the Out is of zero length and has a Data Toggle (DTOG CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... ISR to unlock and get the mode register information. The interlock on the Mode and Count registers ensures that the firmware recognizes the changes that the SIE might have made during the previous transaction. CY7C63413C CY7C63513C CY7C63613C What the SIE does to Mode bits ...
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... UC invalid valid 1 1 updates UC valid 0 1 updates UC valid updates 1 updates invalid valid 1 1 updates UC valid 0 1 updates UC CY7C63413C CY7C63513C CY7C63613C Set End Point Mode In Out ACK response ACK NoChange ignore NoChange ignore NoChange ignore NoChange NAK NoChange NAK NoChange ignore UC UC ...
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... UC x updates updates updates UC updates 0 updates valid updates updates updates CY7C63413C CY7C63513C CY7C63613C Set End Point Mode In Out ACK response Stall ignore ignore Stall ACK NoChange ignore NoChange ignore NoChange ignore NoChange NAK NoChange ignore NoChange ignore UC UC ...
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... K 9.1 K Ohms 45% 65% range, as well as DAC outputs. CC (2) is limited to minimize Ground-Drop noise effects. SS CY7C63413C CY7C63513C CY7C63613C Unit Conditions [4] V Non USB activity [5] V USB activity 5 – A Oscillator off, D– > Voh min V – ...
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... DAC outputs. CC (2) of 50–600 pF. LOAD is limited to minimize Ground-Drop noise effects. SS CY7C63413C CY7C63513C CY7C63613C Conditions All ports, HIGH to LOW edge [9] Port 3, Vout = 1.0 V [9] Port 0,1,2, Vout = 2.0 V [9] Voh = 2.4 V (all ports 0,1,2,3) Note16 [10] Vout = 2 ...
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... V crs V ol D T PERIOD Differential Data Lines Document #: 38-08027 Rev. *E Figure 8. Clock Timing . t CYC Figure 9. USB Data Signal Timing 90% 90% 10% 10% Figure 10. Receiver Jitter Tolerance JR1 Consecutive Transitions PERIOD JR1 Paired Transitions PERIOD JR2 CY7C63413C CY7C63513C CY7C63613C T JR2 Page [+] Feedback ...
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... Document #: 38-08027 Rev. *E Crossover Point Extended Point Diff. Data to SE0 Skew + T PERIOD DEOP Figure 12. Differential Data Jitter Crossover Points Consecutive Transitions PERIOD xJR1 Paired Transitions PERIOD xJR2 CY7C63413C CY7C63513C CY7C63613C Source EOP Width: T EOPT Receiver EOP Width EOPR1 EOPR2 Page [+] Feedback ...
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... Ordering Information EPROM Ordering Code Size CY7C63413C-PVXC 8 KB CY7C63413C-PVXCT 8 KB CY7C63513C-PVXC 8 KB CY7C63613C-SXC 8 KB Ordering Code Definition (T) CY 7C63 XXX XXX C/I Document #: 38-08027 Rev. *E Package Package Type Name SP48 48-pin Shrunk Small Outline Package SP48 48-pin SSOP Pb-free Tape-reel SP48 48-pin SSOP Pb-free SZ24 ...
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... DAC4 516.25 32 Port0[6] 413.25 31 Port0[4] 98.00 30 Port0[2] 98.00 29 Port0[0] 98.00 28 DAC2 98.00 27 DAC0 98.00 26 XtalOut 98.00 25 XtalIn CY7C63413C CY7C63513C CY7C63613C X Y 1619.65 3023.60 1719.65 3023.60 1823.10 3023.60 1926.10 3023.60 2066.30 2657.35 2066.30 2554.35 2066.30 2451.35 2066.30 2348.35 2066.30 2245.35 2066.30 2142.35 2066 ...
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... Package Diagrams Figure 13. 48-Pin Shrunk Small Outline Package Document #: 38-08027 Rev. *E CY7C63413C CY7C63513C CY7C63613C 51-85061 *D Page [+] Feedback ...
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... Figure 14. 24-Pin SOIC (.615X.300X.0932 inches) Document #: 38-08027 Rev. *E CY7C63413C CY7C63513C CY7C63613C 51-85025 *D Page [+] Feedback ...
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... I/O input/output IPOR imprecise power on reset Symbol Unit of Measure W microwatts mA milliampere ms millisecond mV millivolts nA nanoampere ns nanosecond nV nanovolts ohm pA picoampere pF picofarad pp peak-to-peak ppm parts per million ps picosecond sps samples per second s sigma: one standard deviation V volts CY7C63413C CY7C63513C CY7C63613C Page [+] Feedback ...
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... Document History Page Document Title: CY7C63413C, CY7C63513C, CY7C63613C Low-Speed High Input/Output 1.5-Mbps USB Controller Document Number: 38-08027 REV. ECN NO. Issue Date ** 116224 06/12/02 *A 237148 SEE ECN *B 418699 See ECN *C 2896245 03/19/10 *D 3057657 10/13/10 *E 3130046 01/18/2011 Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’ ...