CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 19

• Manufacturer Part Number: CY7C63413C-PVXC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.25V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 1
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P02
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1852

The ‘Acknowledge’ bit is set whenever the SIE engages in a
transaction that completes with an ‘ACK’ packet.
The ‘set-up’ PID status (bit[7]) is forced HIGH from the start of
the data packet phase of the set-up transaction, until the start of
the ACK packet returned by the SIE. The CPU is prevented from
clearing this bit during this interval, and subsequently until the
CPU first does an IORD to this endpoint 0 mode register.
Bits[6:0] of the endpoint 0 mode register are locked from CPU
IOWR operations only if the SIE has updated one of these bits,
which the SIE does only at the end of a packet transaction
(set-up... Data... ACK, or Out... Data... ACK, or In... Data... ACK).
The CPU can unlock these bits by doing a subsequent I/O read
of this register.
Firmware must do an IORD after an IOWR to an endpoint 0
register to verify that the contents have changed and that the SIE
has not updated these values.
Table 21. USB Device Counter Registers
Document #: 38-08027 Rev. *E
Addr: 0x11, 0x13, 0x15
Data 0/1
Toggle
R/W
Data Valid
R/W
Reserved
R/W
USB Device Counter Registers
Reserved
R/W
Byte count
While the ‘set-up’ bit is set, the CPU cannot write to the DMA
buffers at memory locations 0xE0 through 0xE7 and 0xF8
through 0xFF. This prevents an incoming set-up transaction from
conflicting with a previous In data buffer filling operation by
firmware.
The mode bits (bits [3:0]) in an Endpoint Mode Register control
how the endpoint responds to USB bus traffic. The mode bit
encoding is shown in Section .
The format of the endpoint Device counter registers is shown in
Table
Bits 0 to 3 indicate the number of data bytes to be transmitted
during an IN packet, valid values are 0 to 8 inclusive. Data Valid
bit 6 is used for OUT and set-up tokens only. Data 0/1 Toggle bit
7 selects the DATA packet’s toggle state: 0 for DATA0, 1 for
DATA1.
Bit 3
R/W
21.
Byte count
Bit 2
R/W
Byte count
Bit 1
R/W
CY7C63413C
CY7C63513C
CY7C63613C
Byte count
Bit 0
R/W
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