CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 11

• Manufacturer Part Number: CY7C63413C-PVXC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.25V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 1
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P02
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1852

Clocking
The XTAL
microcontroller. The user can connect a low-cost ceramic
resonator or an external oscillator can be connected to these
pins to provide a reference frequency for the internal clock
distribution and clock doubler.
An external 6-MHz clock can be applied to the XTAL
XTAL
XTAL
shorted to ground.
Reset
The USB Controller supports three types of resets. All registers
are restored to their default states during a reset. The USB
Device Addresses are set to 0 and all interrupts are disabled. In
addition, the program stack pointer (PSP) and data stack pointer
(DSP) are set to 0x00. For USB applications, the firmware should
set the DSP below 0xE8 to avoid a memory conflict with RAM
dedicated to USB FIFOs. The assembly instructions to do this
are shown below:
The three reset types are:
The occurrence of a reset is recorded in the Processor Status
and Control Register located at I/O address 0xFF. Bits 4, 5, and
6 are used to record the occurrence of POR, USB Reset, and
WDR respectively. The firmware can interrogate these bits to
determine the cause of a reset.
The microcontroller begins execution from ROM address 0x0000
after a POR or WDR reset. Although this looks like interrupt
vector 0, there is an important difference. Reset processing does
NOT push the program counter, carry flag, and zero flag onto
program stack. That means the reset handler in firmware should
initialize the hardware and begin executing the “main” loop of
code. Attempting to execute either a RET or RETI in the reset
handler will cause unpredictable execution results.
Power-On Reset (POR)
Power-On Reset (POR) occurs every time the V
device ramps from 0V to an internally defined trip voltage (Vrst)
Document #: 38-08027 Rev. *E
1. Power-On Reset (POR)
2. Watch Dog Reset (WDR)
3. USB Bus Reset (non hardware reset)
Mov A, E8h
Swap A,dsp
OUT
OUT
pin is not permissible as the internal clock is effectively
pin is left open. Please note that grounding the
IN
and XTAL
; Move 0xE8 hex into Accumulator
; Swap accumulator value into dsp register
OUT
Clock Distribution
(to Microcontroller)
are the clock pins to the
(to USB SIE)
clk1x
clk2x
Figure 2. Clock Oscillator On-chip Circuit
CC
Doubler
voltage to the
Clock
IN
pin if the
30 pF
of approximately 1/2 full supply voltage. In addition to the normal
reset initialization noted under “Reset,” bit 4 (PORS) of the
Processor Status and Control Register is set to “1” to indicate to
the firmware that a Power-On Reset occurred. The POR event
forces the GPIO ports into input mode (high impedance), and the
state of Port 3 bit 7 is used to control how the part will respond
after the POR releases.
If Port 3 bit 7 is HIGH (pulled to V
idle state (DM HIGH and DP LOW) the part will go into a
semi-permanent power down/suspend mode, waiting for the
USB I/O to go to one of Bus Reset, K (resume) or SE0. If Port 3
bit 7 is still HIGH when the part comes out of suspend, then a
128-s timer starts, delaying CPU operation until the ceramic
resonator has stabilized.
If Port 3 bit 7 was LOW (pulled to V
timer, delaying CPU operation until V
continuing to run as reset.
Firmware should clear the POR Status (PORS) bit in register
0xFF before going into suspend as this status bit selects the
128-s or 96-ms start-up timer value as follows: IF Port 3 bit 7 is
HIGH then 128-s is always used; ELSE if PORS is HIGH then
96-ms is used; ELSE 128-s is used.
Watch Dog Reset (WDR)
The Watch Dog Timer Reset (WDR) occurs when the Most
Significant Bit (MSB) of the 2-bit Watch Dog Timer Register
transitions from LOW to HIGH. In addition to the normal reset
initialization noted under “Reset,” bit 6 of the Processor Status
and Control Register is set to “1” to indicate to the firmware that
a Watch Dog Reset occurred.
The Watch Dog Timer is a 2-bit timer clocked by a 4.096-ms
clock (bit 11) from the free-running timer. Writing any value to the
write-only Watch Dog Clear I/O port (0x26) will clear the Watch
Dog Timer.
In some applications, the Watch Dog Timer may be cleared in
the 1.024-ms timer interrupt service routine. If the 1.024-ms timer
interrupt service routine does not get executed for 8.192 ms or
more, a Watch Dog Timer Reset will occur. A Watch Dog Timer
Reset lasts for 2.048 ms after which the microcontroller begins
execution at ROM address 0x0000. The USB transmitter is
disabled by a Watch Dog Reset because the USB Device
Address Register is cleared. Otherwise, the USB Controller
would respond to all address 0 transactions. The USB
transmitter remains disabled until the MSB of the USB address
register is set.
30 pF
XTALOUT
XTALIN
CC
SS
) and the USB I/O are at the
) the part will start a 96-ms
CC
has stabilized, then
CY7C63413C
CY7C63513C
CY7C63613C
Page 11 of 36
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