CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 28

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CY7C63413C-PVXC

Manufacturer Part Number
CY7C63413C-PVXC
Description
IC MCU 8K USB LS PERIPH 48-SSOP
Manufacturer
Cypress Semiconductor Corp
Series
M8™r
Datasheets

Specifications of CY7C63413C-PVXC

Applications
USB Microcontroller
Core Processor
M8B
Program Memory Type
OTP (8 kB)
Controller Series
CY7C634xx
Ram Size
256 x 8
Interface
PS2, USB
Number Of I /o
32
Voltage - Supply
4 V ~ 5.5 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-SSOP
No. Of I/o's
32
Ram Memory Size
256Byte
Cpu Speed
12MHz
No. Of Timers
2
Digital Ic Case Style
SSOP
Supply Voltage Range
4V To 5.25V
Core Size
8 Bit
Program Memory Size
8KB
Embedded Interface Type
USB
Rohs Compliant
Yes
Processor Series
CY7C63xx
Core
M8B
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
PS2, USB
Maximum Clock Frequency
12 MHz
Number Of Programmable I/os
32
Number Of Timers
1
Operating Supply Voltage
4 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3654, CY3654-P02
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
428-1852

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Manufacturer:
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DC Characteristics
Switching Characteristics
Notes
Document #: 38-08027 Rev. *E
V
I
I
I
R
I
I
I
I
I
I
t
T
9. Functionality is guaranteed of the V
10. USB transmitter functionality is guaranteed over the V
11. Per Table 7-7 of revision 1.1 of USB specification, for C
12. Measured as largest step size vs. nominal according to measured full scale and zero programmed values.
13. T
14. Irange: Isinkn(15)/ Isinkn(0) for the same pin.
15. Measured at crossover point of differential data signals.
16. Limits total bus capacitance loading (C
17. DAC I/O Port not bonded out on CY7C63613C. See note on page 12 for firmware code needed for unused pins.
18. Total current cumulative across all Port pins flowing to V
t
t
t
t
t
t
t
t
V
t
t
t
t
t
t
t
t
t
ol
ol
oh
sink0(0)
sink0(F)
sink1(0)
sink1(F)
range
lin
sink
Parameter
CYC
CH
CL
r
r
f
f
rfm
drate
djr1
djr2
deop
eopr1
eopr2
eopt
udj1
udj2
DAC Interface
ratio
H
Clock
USB Driver Characteristics
USB Data Timing
up
crs
ratio
= Isink1[1:0](n)/Isink0[7:2](n) for the same n, programmed.
Input hysteresis voltage
Sink current
Sink current
Source current
Pull-up resistance
DAC[7:2] sink current (0)
DAC[7:2] sink current (F)
DAC[1:0] sink current (0)
DAC[1:0] sink current (F)
Programmed Isink ratio: max/min
Differential nonlinearity
Current sink response time
Tracking ratio DAC[1:0] to DAC[7:2]
Input Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Transition Rise Time
Transition Rise Time
Transition Fall Time
Transition Fall Time
Rise/Fall Time Matching
Output Signal Crossover Voltage
Low Speed Data Rate
Receiver Data Jitter Tolerance
Receiver Data Jitter Tolerance
Differential to EOP Transition Skew
EOP Width at Receiver
EOP Width at Receiver
Source EOP Width
Differential Driver Jitter
Differential Driver Jitter
Fosc = 6 MHz; operating temperature = 0 to 70 °C (continued)
CC (1)
Description
Parameter
LOAD
range, except USB transmitter and DACs.
) to 400 pF per section 7.1.5 of revision 1.1 of USB specification.
[17]
[17]
[17]
[17]
CC (2)
LOAD
SS
is limited to minimize Ground-Drop noise effects.
range, as well as DAC outputs.
of 50–600 pF.
1.4775
8.0 K
165.0
–150
t
t
Min
0.45
0.45
1.25
Min
330
675
–95
6%
7.2
3.5
1.4
0.1
0.5
1.6
–75
–45
–40
CYC
CYC
1.3
14
75
75
80
8
4
20.0 K
1.5225
168.3
12%
Max
16.5
10.6
Max
1.50
300
300
125
100
150
7.5
0.3
1.5
4.8
0.5
0.8
2.0
24
21
75
45
95
6
Ohms
Unit
V
Unit
Mbs
mA
mA
mA
mA
mA
mA
mA
lsb
s
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
%
CC
V
Voh = 2.4 V (all ports 0,1,2,3)
Vout = 2.0 VDC
All ports, HIGH to LOW edge
Port 3, Vout = 1.0 V
Port 0,1,2, Vout = 2.0 V
Note16
Vout = 2.0 VDC
Vout = 2.0 DC
Vout = 2.0 VDC
Vout = 2.0 VDC
Any pin
Full scale transition
Vout = 2.0 V
CLoad = 50 pF
CLoad = 600 pF
CLoad = 50 pF
CLoad = 600 pF
t
Notes 10 and 11
Ave. Bit Rate (1.5 Mb/s ± 1.5%)
To Next Transition
For Paired Transitions
Note 18
Rejects as EOP
Accepts as EOP
To next transition,
To paired transition,
r
/t
f
[10, 11]
[12]
[13]
Conditions
Conditions
[10]
[10, 11]
[10, 11]
[10]
[10]
[10]
[10,14]
[15]
[10, 11]
[15]
[10, 11]
CY7C63413C
CY7C63513C
CY7C63613C
Figure 12 on page
[15]
Figure 12 on page
[9]
[15]
[9]
Page 28 of 36
[9]
30.
30.
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