CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 21

• Manufacturer Part Number: CY7C63413C-PVXC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.25V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 1
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P02
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1852

Processor Status and Control Register
Table 24. Processor Status and Control Register
The “Run” (bit 0) is manipulated by the HALT instruction. When
Halt is executed, the processor clears the run bit and halts at the
end of the current instruction. The processor remains halted until
a reset (Power On or Watch Dog). Notice, when writing to the
processor status and control register, the run bit should always
be written as a “1.”
The “Single Step” (bit 1) is provided to support a hardware
debugger. When single step is set, the processor will execute
one instruction and halt (clear the run bit). This bit must be
cleared for normal operation.
The “Interrupt Mask” (bit 2) shows whether interrupts are
enabled or disabled. The firmware has no direct control over this
bit as writing a zero or one to this bit position will have no effect
on interrupts. Instructions DI, EI, and RETI manipulate the
internal hardware that controls the state of the interrupt mask bit
in the Processor Status and Control Register.
Writing a “1” to “Suspend, Wait for Interrupts” (bit 3) will halt the
processor and cause the microcontroller to enter the “suspend”
mode that significantly reduces power consumption. A pending
interrupt or bus activity will cause the device to come out of
suspend. After coming out of suspend, the device will resume
firmware execution at the instruction following the IOWR which
put the part into suspend. An IOWR that attempts to put the part
into suspend will be ignored if either bus activity or an interrupt
is pending.
The “Power-on Reset” (bit 4) is only set to “1” during a power on
reset. The firmware can check bits 4 and 6 in the reset handler
to determine whether a reset was caused by a Power On
condition or a Watch Dog Timeout. PORS is used to determine
suspend start-up timer value of 128 s or 96 ms.
The “USB Bus Reset” (bit 5) will occur when a USB bus reset is
received. The USB Bus Reset is a singled-ended zero (SE0) that
lasts more than 8 microseconds. An SE0 is defined as the
condition in which both the D+ line and the D– line are LOW at
the same time. When the SIE detects this condition, the USB Bus
Reset bit is set in the Processor Status and Control register and
an USB Bus Reset interrupt is generated. Please note this is an
interrupt to the microcontroller and does not actually reset the
processor.
The “Watch Dog Reset” (bit 6) is set during a reset initiated by
the Watch Dog Timer. This indicates the Watch Dog Timer went
for more than 8 ms between watch dog clears.
Document #: 38-08027 Rev. *E
Pending
IRQ
R
7
Addr: 0xFF
Watch Dog
Reset
R/W
6
USB Bus
Reset
R/W
5
Processor Status and Control Register
Power-on
Reset
R/W
4
Suspend, Wait
for Interrupt
The “IRQ Pending” (bit 7) indicates one or more of the interrupts
has been recognized as active. The interrupt acknowledge
sequence should clear this bit until the next interrupt is detected.
During Power-on Reset, the Processor Status and Control
Register is set to 00010001, which indicates a Power-on Reset
(bit 4 set) has occurred and no interrupts are pending (bit 7 clear)
yet.
During a Watch Dog Reset, the Processor Status and Control
Register is set to 01000001, which indicates a Watch Dog Reset
(bit 6 set) has occurred and no interrupts are pending (bit 7 clear)
yet.
Interrupts
All interrupts are maskable by the Global Interrupt Enable
Register and the USB End Point Interrupt Enable Register.
Writing a “1” to a bit position enables the interrupt associated with
that bit position. During a reset, the contents the Global Interrupt
Enable Register and USB End Point Interrupt Enable Register
are cleared, effectively disabling all interrupts.
Pending interrupt requests are recognized during the last clock
cycle of the current instruction. When servicing an interrupt, the
hardware will first disable all interrupts by clearing the Interrupt
Enable bit in the Processor Status and Control Register. Next,
the interrupt latch of the current interrupt is cleared. This is
followed by a CALL instruction to the ROM address associated
with the interrupt being serviced (i.e., the Interrupt Vector). The
instruction in the interrupt table is typically a JMP instruction to
the address of the Interrupt Service Routine (ISR). The user can
re-enable interrupts in the interrupt service routine by executing
an EI instruction. Interrupts can be nested to a level limited only
by the available stack space.
The Program Counter value as well as the Carry and Zero flags
(CF, ZF) are automatically stored onto the Program Stack by the
CALL instruction as part of the interrupt acknowledge process.
The user firmware is responsible for insuring that the processor
state is preserved and restored during an interrupt. The PUSH A
instruction should be used as the first command in the ISR to
save the accumulator value and the POP A instruction should be
used just before the RETI instruction to restore the accumulator
value. The program counter CF and ZF are restored and
interrupts are enabled when the RETI instruction is executed.
R/W
3
Interrupt
Mask
R
2
Single Step
POR Default: 0x0101
R/W
WDC Reset: 0x41
1
CY7C63413C
CY7C63513C
CY7C63613C
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R/W
Run
0
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