CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 23

• Manufacturer Part Number: CY7C63413C-PVXC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.25V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 1
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P02
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1852

interrupt priority to different DAC pins and the DAC Interrupt
Enable Register is not cleared during the interrupt acknowledge
process.
GPIO Interrupt
Each of the 32 GPIO pins can generate an interrupt, if enabled.
The interrupt polarity can be programmed for each GPIO port as
part of the GPIO configuration. All of the GPIO pins share a
single interrupt vector, which means the firmware will need to
Truth Tables
Table 27. USB Register Mode Encoding
The ‘In’ column represents the SIE’s response to the token type.
A disabled endpoint will remain such until firmware changes it,
and all endpoints reset to disabled.
Any Setup packet to an enabled and accepting endpoint will be
changed by the SIE to 0001 (NAKing). Any mode which indicates
the acceptance of a Setup will acknowledge it.
Most modes that control transactions involving an ending ACK
will be changed by the SIE to a corresponding mode which NAKs
follow on packets.
Document #: 38-08027 Rev. *E
Mode
Disable
Nak In/Out
Status Out Only
Stall In/Out
Ignore In/Out
Isochronous Out
Status In Only
Isochronous In
Nak Out
Ack Out
Nak Out - Status In
Ack Out - Status In
Nak In
Ack In
Nak In - Status Out
Ack In - Status Out
Encoding
0000
0001
0010
0100
0101
1000
1001
1010
0011
0110
0111
1011
1100
1101
1110
1111
accept
accept
accept
accept
accept
accept
accept
accept
accept
Setup
ignore
ignore
ignore
ignore
ignore
ignore
ignore
TX cnt
TX cnt
TX cnt
ignore
ignore
ignore
ignore
ignore
NAK
TX 0
TX 0
TX 0
NAK
NAK
stall
stall
In
always
ignore
ignore
ignore
ignore
ignore
Check
check
check
NAK
NAK
ACK
NAK
ACK
Out
stall
stall
Forced from Set-up on Control endpoint, from modes other
For Control endpoints
For Control endpoints
For Control endpoints
Available to low speed devices, future USB spec
An ACK from mode 1001 --> 1000
This mode is changed by SIE on issuance of ACK --> 1000
Comments
Ignore all USB traffic to this endpoint
than 0000
enhancements
For Control Endpoints
Available to low speed devices, future USB spec
enhancements
An ACK from mode 1011 --> 1010
This mode is changed by SIE on issuance of ACK --> 1010
An ACK from mode 1101 --> 1100
This mode is changed by SIE on issuance of ACK --> 1100
An ACK from mode 1111 --> 1110 NAck In - Status Out
This mode is changed by SIE on issuance of ACK -->1110
read the GPIO ports with enabled interrupts to determine which
pin or pins caused an interrupt.
Please note that if one port pin triggered an interrupt, no other
port pins can cause a GPIO interrupt until that port pin has
returned to its inactive (non-trigger) state or its corresponding
port interrupt enable bit is cleared. The USB Controller does not
assign interrupt priority to different port pins and the Port
Interrupt Enable Registers are not cleared during the interrupt
acknowledge process.
A Control endpoint has three extra status bits for PID (Setup, In
and Out), but must be placed in the correct mode to function as
such. Also a non-Control endpoint can be made to act as a
Control endpoint if it is placed in a non appropriate mode.
A ‘check’ on an Out token during a Status transaction checks to
see that the Out is of zero length and has a Data Toggle (DTOG)
of 1.
CY7C63413C
CY7C63513C
CY7C63613C
Page 23 of 36
[+] Feedback