CY7C63413C-PVXC Cypress Semiconductor Corp, CY7C63413C-PVXC Datasheet - Page 6

• Manufacturer Part Number: CY7C63413C-PVXC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• No. Of I/o's: 32
• Ram Memory Size: 256Byte
• Cpu Speed: 12MHz
• No. Of Timers: 2
• Digital Ic Case Style: SSOP
• Supply Voltage Range: 4V To 5.25V
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: USB
• Rohs Compliant: Yes
• Processor Series: CY7C63xx
• Core: M8B
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: PS2, USB
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 1
• Operating Supply Voltage: 4 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P02
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 428-1852

PSP,A instruction. The PSP supports interrupt service under
hardware control and CALL, RET, and RETI instructions under
firmware control.
During an interrupt acknowledge, interrupts are disabled and the
14-bit program counter, carry flag, and zero flag are written as
two bytes of data memory. The first byte is stored in the memory
addressed by the program stack pointer, then the PSP is
incremented. The second byte is stored in memory addressed
by the program stack pointer and the PSP is incremented again.
The net effect is to store the program counter and flags on the
program “stack” and increment the program stack pointer by two.
The Return From Interrupt (RETI) instruction decrements the
program stack pointer, then restores the second byte from
memory addressed by the PSP. The program stack pointer is
decremented again and the first byte is restored from memory
addressed by the PSP. After the program counter and flags have
been restored from stack, the interrupts are enabled. The effect
is to restore the program counter and flags from the program
stack, decrement the program stack pointer by two, and
re-enable interrupts.
The Call Subroutine (CALL) instruction stores the program
counter and flags on the program stack and increments the PSP
by two.
The Return From Subroutine (RET) instruction restores the
program counter, but not the flags, from program stack and
decrements the PSP by two.
8-bit Data Stack Pointer (DSP)
The Data Stack Pointer (DSP) supports PUSH and POP
instructions that use the data stack for temporary storage. A
PUSH instruction will pre-decrement the DSP, then write data to
the memory location addressed by the DSP. A POP instruction
will read data from the memory location addressed by the DSP,
then post-increment the DSP.
During a reset, the Data Stack Pointer will be set to zero. A PUSH
instruction when DSP equal zero will write data at the top of the
data RAM (address 0xFF). This would write data to the memory
area reserved for a FIFO for USB endpoint 0. In non-USB
applications, this works fine and is not a problem. For USB
applications, it is strongly recommended that the DSP is loaded
after reset just below the USB DMA buffers.
Address Modes
The CY7C63413C/513C/613C microcontrollers support three
addressing modes for instructions that require data operands:
data, direct, and indexed.
Document #: 38-08027 Rev. *E
Data
The “Data” address mode refers to a data operand that is actually
a constant encoded in the instruction. As an example, consider
the instruction that loads A with the constant 0xE8:
■
This instruction will require two bytes of code where the first byte
identifies the “MOV A” instruction with a data operand as the
second byte. The second byte of the instruction will be the
constant “0xE8”. A constant may be referred to by name if a prior
“EQU” statement assigns the constant value to the name. For
example, the following code is equivalent to the example shown
above:
■
■
Direct
“Direct” address mode is used when the data operand is a
variable stored in SRAM. In that case, the one byte address of
the variable is encoded in the instruction. As an example,
consider an instruction that loads A with the contents of memory
address location 0x10:
■
In normal usage, variable names are assigned to variable
addresses using “EQU” statements to improve the readability of
the assembler source code. As an example, the following code
is equivalent to the example shown above:
■
■
Indexed
“Indexed” address mode allows the firmware to manipulate
arrays of data stored in SRAM. The address of the data operand
is the sum of a constant encoded in the instruction and the
contents of the “X” register. In normal usage, the constant will be
the “base” address of an array of data and the X register will
contain an index that indicates which element of the array is
actually addressed:
■
■
■
This would have the effect of loading A with the fourth element
of the SRAM “array” that begins at address 0x10. The fourth
element would be at address 0x13.
MOV A,0E8h
DSPINIT: EQU 0E8h
MOV A,DSPINIT
MOV A, [10h]
buttons: EQU 10h
MOV A,[buttons]
array: EQU 10h
MOV X,3
MOV A,[x+array]
CY7C63413C
CY7C63513C
CY7C63613C
Page 6 of 36
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