CY7C65113C-SXC Cypress Semiconductor Corp, CY7C65113C-SXC Datasheet - Page 19

• Manufacturer Part Number: CY7C65113C-SXC
• Description: IC MCU 8K FULL SPEED USB 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 11
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-2259-5; CY7C65113C-SXC

Bits [7..0]: I
The I
Table 6. I
Bit 7: MSTR Mode
Document #: 38-08002 Rev. *F
I
Bit #
Bit Name
Read/Write
Reset
2
Bit
C Status and Control
0
1
2
3
4
5
6
7
2
Contains the 8-bit data on the I
Setting this bit to 1 causes the I
tiate a master mode transaction by sending a start bit and
transmitting the first data byte from the data register (this
typically holds the target address and R/W bit). Subse-
quent bytes are initiated by setting the Continue bit, as
described below.
Clearing this bit (set to 0) causes the GPIO pins to operate
normally.
In master mode, the I
clock (SCK), and drives the data line as required depend-
ing on transmit or receive state. The I
performs any required arbitration and clock synchroniza-
tion. IN the event of a loss of arbitration, this MSTR bit is
cleared, the ARB Lost bit is set, and an interrupt is gener-
ated by the microcontroller. If the chip is the target of an
external master that wins arbitration, then the interrupt is
held off until the transaction from the external master is
completed.
When MSTR Mode is cleared from 1 to 0 by a firmware
write, an I
C Status and Control register bits are defined in
2
I
Received Stop
ARB Lost/Restart Reads 1 to indicate master has lost arbitration. Reads 0 otherwise.
Addr
ACK
Xmit Mode
Continue/Busy
MSTR Mode
C Status and Control Register Bit Definitions
2
2
C Enable
C Data
2
Name
C Stop bit is generated.
MSTR Mode Continue/Bu
R/W
7
0
2
C-compatible block generates the
When set to ‘1’, the I
normally.
Reads 1 only in slave receive mode, when I
last transaction).
Write to 1 in master mode to perform a restart sequence (also set Continue bit).
Reads 1 during first byte after start/restart in slave mode, or if master loses arbitration.
Reads 0 otherwise. This bit should always be written as 0.
In receive mode, write 1 to generate ACK, 0 for no ACK.
In transmit mode, reads 1 if ACK was received, 0 if no ACK received.
Write to 1 for transmit mode, 0 for receive mode.
Write 1 to indicate ready for next transaction.
Reads 1 when I
Write to 1 for master mode, 0 for slave mode. This bit is cleared if master loses arbitration.
Clearing from 1 to 0 generates Stop bit.
R/W
sy
6
0
2
2
C Bus
C-compatible block to ini-
Figure 16. I
2
C-compatible block
2
Xmit Mode
C-compatible block is busy with a transaction, 0 when transaction is complete.
R/W
2
5
0
C-compatible function is enabled. When cleared, I
Table
2
C Status and Control Register.
6, with a more detailed description following.
ACK
R/W
4
0
Bit 6: Continue/Busy
Bit 5: Xmit Mode
Description
2
C Stop bit detected (unless firmware did not ACK the
This bit is written by the firmware to indicate that the firm-
ware is ready for the next byte transaction to begin. In oth-
er words, the bit has responded to an interrupt request and
has completed the required update or read of the data reg-
ister. During a read this bit indicates if the hardware is busy
and is locking out additional writes to the I
Control register. This locking allows the hardware to com-
plete certain operations that may require an extended pe-
riod of time. Following an I
block does not return to the Busy state until firmware sets
the Continue bit. This allows the firmware to make one
control register write without the need to check the Busy
bit.
This bit is set by firmware to enter transmit mode and per-
form a data transmit in master or slave mode. Clearing this
bit sets the part in receive mode. Firmware generally de-
termines the value of this bit from the R/W bit associated
with the I
ignored when initially writing the MSTR Mode or the Re-
Addr
R/W
3
0
2
C address packet. The Xmit Mode bit state is
Lost/Restart
ARB
R/W
2
0
2
C interrupt, the I
2
C GPIO pins operate
Received
Stop
R/W
1
0
CY7C65113C
Address 0x28
I
2
2
2
Page 19 of 48
C-compatible
C Enable
C Status and
R/W
0
0
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