CY7C65113C-SXC Cypress Semiconductor Corp, CY7C65113C-SXC Datasheet - Page 22

• Manufacturer Part Number: CY7C65113C-SXC
• Description: IC MCU 8K FULL SPEED USB 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 11
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-2259-5; CY7C65113C-SXC

Bit 0: EPA0 Interrupt Enable
Bit 1: EPA1 Interrupt Enable
Bit 2: EPA2 Interrupt Enable
Bit 3: EPB0 Interrupt Enable
Bit 4: EPB1 Interrupt Enable
Bit [7..5]: Reserved
During a reset, the contents of the Global Interrupt Enable
Register and USB End Point Interrupt Enable Register are
cleared, effectively disabling all interrupts,
The interrupt controller contains a separate flip-flop for each
interrupt. See
interrupt controller. When an interrupt is generated, it is first
registered as a pending interrupt. It stays pending until it is
serviced or a reset occurs. A pending interrupt only generates an
interrupt request if it is enabled by the corresponding bit in the
interrupt enable registers. The highest priority interrupt request
is serviced following the completion of the currently executing
instruction.
When servicing an interrupt, the hardware does the following:
Document #: 38-08002 Rev. *F
1 = Enable Interrupt on data activity through endpoint A0;
0 = Disable Interrupt on data activity through endpoint A0
1 = Enable Interrupt on data activity through endpoint A1;
0 = Disable Interrupt on data activity through endpoint A1
1 = Enable Interrupt on data activity through endpoint A2;
0 = Disable Interrupt on data activity through endpoint A2.
1 = Enable Interrupt on data activity through endpoint B0;
0 = Disable Interrupt on data activity through endpoint B0
1 = Enable Interrupt on data activity through endpoint B1;
0 = Disable Interrupt on data activity through endpoint B1
Figure 20
for the logic block diagram of the
The instruction in the interrupt table is typically a JMP instruction
to the address of the Interrupt Service Routine (ISR). The user
can reenable interrupts in the interrupt service routine by
executing an EI instruction. Interrupts can be nested to a level
limited only by the available stack space.
The Program Counter value as well as the Carry and Zero flags
(CF, ZF) are stored onto the Program Stack by the automatic
CALL instruction generated as part of the interrupt acknowledge
process. The user firmware is responsible for ensuring that the
processor state is preserved and restored during an interrupt.
The PUSH A instruction should typically be used as the first
command in the ISR to save the accumulator value and the POP
A instruction should be used to restore the accumulator value
just before the RETI instruction. The program counters CF and
ZF are restored and interrupts are enabled when the RETI
instruction is executed.
The IDI and EI instruction can be used to disable and enable
interrupts, respectively. These instruction affect only the Global
Interrupt Enable bit of the CPU. If desired, EI can be used to
re-enable interrupts while inside an ISR, instead of waiting for the
RETI that exits the ISR. While the global interrupt enable bit is
cleared, the presence of a pending interrupt can be detected by
examining the IRQ Sense bit (Bit 7 in the Processor Status and
Control Register).
1. Disables all interrupts by clearing the Global Interrupt Enable
2. Clears the flip-flop of the current interrupt.
3. Generates an automatic CALL instruction to the ROM
bit in the CPU (the state of this bit can be read at Bit 2 of the
Processor Status and Control Register, Figure 17).
address associated with the interrupt being serviced (i.e., the
Interrupt Vector, see Section ).
CY7C65113C
Page 22 of 48
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