CY7C65113C-SXC Cypress Semiconductor Corp, CY7C65113C-SXC Datasheet - Page 33

• Manufacturer Part Number: CY7C65113C-SXC
• Description: IC MCU 8K FULL SPEED USB 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 11
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-2259-5; CY7C65113C-SXC

Bits[6:0] of the endpoint 0 mode register are locked from CPU
write operations whenever the SIE has updated one of these bits,
which the SIE does only at the end of the token phase of a trans-
action (SETUP... Data... ACK, OUT... Data... ACK, or IN... Data...
ACK). The CPU can unlock these bits by doing a subsequent
read of this register. Only endpoint 0 mode registers are locked
when updated. The locking mechanism does not apply to the
mode registers of other endpoints.
Bits[3..0]: Mode.
Bit 4: ACK.
Bits[6..5]: Reserved.
Document #: 38-08002 Rev. *F
Note
Note
4. In 5-endpoint mode (USB Status And Control Register Bits [7,6] are set to [0,1] or [1,1]), Register 0x42 serves as non-control endpoint 3, and has the format for
5. The SIE offers an “Ack out – Status in” mode and not an “Ack out – Nak in” mode. Therefore, if following the status stage of a Control Write transfer a USB host
Bit #
Bit Name
Read/Write
Reset
USB Endpoint Counter
Bit #
Bit Name
Read/Write
Reset
non-control endpoints shown in Figure 34.
were to immediately start the next transfer, the new Setup packet could override the data payload of the data stage of the previous Control Write.
report the type of token received by the corresponding de-
vice address is a SETUP token. Any write to this bit by the
CPU will clear it (set it to 0). The bit is forced HIGH from
the start of the data packet phase of the SETUP transac-
tion until the start of the ACK packet returned by the SIE.
The CPU should not clear this bit during this interval, and
subsequently, until the CPU first does an IORD to this end-
point 0 mode register. The bit must be cleared by firmware
as part of the USB processing.
These sets the mode which control how the control end-
point responds to traffic. The mode bit encoding is shown
in
This bit is set whenever the SIE engages in a transaction
to the register’s endpoint that completes with an ACK
packet.
Must be written zero during register writes.
Table
USB Non-control Device Endpoint Mode
11.
Data 0/1
STALL
Toggle
R/W
R/W
7
0
7
0
Data Valid
Reserved
Figure 34. USB Non-control Device Endpoint Mode Registers
R/W
R/W
[4]
6
0
6
0
Figure 35. USB Endpoint Counter Registers
Byte Count
Reserved
Bit 5
R/W
R/W
5
0
5
0
Byte Count
ACK
Bit 4
R/W
R/W
4
0
4
0
Because of these hardware locking features, firmware must
perform an IORD after an IOWR to an endpoint 0 register. This
verifies that the contents have changed as desired, and that the
SIE has not updated these values.
While the SETUP bit is set, the CPU cannot write to the endpoint
zero FIFOs. This prevents firmware from overwriting an incoming
SETUP transaction before firmware has a chance to read the
SETUP data. Refer to
memory locations.
The Mode bits (bits [3:0]) control how the endpoint responds to
USB bus traffic. The mode bit encoding is shown in
Additional information on the mode bits can be found in
and
USB Non-control Endpoint Mode Registers
The format of the non-control endpoint mode registers is shown
in Figure 34.
Bit 7: STALL.
USB Endpoint Counter Registers
There are five Endpoint Counter registers, with identical formats
for both control and non-control endpoints. These registers
contain byte count information for USB transactions, as well as
bits for data packet status. The format of these registers is shown
in Figure 35.
Table
If this STALL is set, the SIE stalls an OUT packet if the
mode bits are set to ACK-IN, and the SIE stalls an IN pack-
et if the mode bits are set to ACK-OUT. For all other
modes, the STALL bit must be a LOW.
Byte Count
Mode Bit 3
Bit 3
R/W
R/W
13.
3
0
3
0
[5]
Addresses 0x11, 0x13, 0x15, 0x41, 0x43
Byte Count
Mode Bit 2
Table 10
Bit 2
R/W
R/W
Addresses 0x14, 0x16, 0x44
2
0
2
0
for the appropriate endpoint zero
Byte Count
Mode Bit 1
R/W
Bit 1
R/W
1
0
1
0
CY7C65113C
Byte Count
Mode Bit 0
Page 33 of 48
Table
R/W
Bit 0
R/W
0
0
0
0
Table 12
11.
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