CY7C65113C-SXC Cypress Semiconductor Corp, CY7C65113C-SXC Datasheet - Page 30

• Manufacturer Part Number: CY7C65113C-SXC
• Description: IC MCU 8K FULL SPEED USB 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 11
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-2259-5; CY7C65113C-SXC

Bit [0..3]: Port x Selective Suspend (where x = 1..4).
Bit 7: Device Remote Wakeup.
Bit [0..3] : Resume x (where x = 1..4).
Bit [4..7]: Reserved.
Resume from a selectively suspended port, with the hub not in
suspend, typically involves the following actions:
Document #: 38-08002 Rev. *F
1. Hardware detects the Resume, drives a K to the port, and
2. Firmware responds to hub interrupt, and reads register 0x4E
3. Firmware begins driving K on the port for 10 ms or more
4. Firmware clears the Selective Suspend bit for the port (0x4D),
5. Firmware drives a timed SE0 on the port for two low-speed bit
6. Firmware drives a J on the port for one low-speed bit time,
7. Firmware re-enables the port.
Hub Ports Suspend
Bit #
Bit Name
Read/Write
Reset
Hub Ports Resume
Bit #
Bit Name
Read/Write
Reset
generates the hub interrupt. The corresponding bit in the Re-
sume Status Register (0x4E) reads ‘1’ in this case.
to determine the source of the Resume.
through register 0x4B.
which clears the Resume bit (0x4E). This ends the
hardware-driven Resume, but the firmware-driven Resume
continues. To prevent traffic being fed by the hub repeater to
the port during or just after the Resume, firmware should
disable this port.
times as appropriate. Firmware must disable interrupts during
this SE0 so the SE0 pulse isn’t inadvertently lengthened, and
appear as a bus reset to the downstream device.
then it idles the port.
Set to 1 if Port x is Selectively Suspended; Set to 0 if Port
x Do not suspend.
When set to 1 Port x requesting to be resumed (set by
hardware); default state is 0.
Set to 0.
Reserved
Wakeup
Remote
Device
R/W
7
0
7
0
-
Reserved
Reserved
R/W
6
0
6
0
-
Figure 30. Hub Ports Resume Status Register
Figure 29. Hub Ports Suspend Register
Reserved
Reserved
R/W
5
0
5
0
-
Reserved
Reserved
R/W
4
0
4
0
-
Resume when the hub is suspended typically involves these
actions:
Firmware can choose to clear the Device Remote Wake-up bit (if
set) to implement firmware timed states for port changes. All
allowed port changes wake the part. Then, the part can use
internal timing to determine whether to take action or return to
suspend. If Device Remote Wake-up is set, automatic hardware
assertions take place on Resume events.
USB Upstream Port Status and Control
USB status and control is regulated by the USB Status and
Control Register, as shown in
cleared during reset.
1. Hardware detects the Resume, drives a K on the upstream
2. The part comes out of suspend and the clocks start.
3. Once the clocks are stable, firmware execution resumes. An
4. The Resume ends when the host stops sending K from
(which is then reflected to all downstream enabled ports), and
generates the hub interrupt.
internal counter ensures that this takes at least 1 ms.
Firmware should check for Resume from any selectively
suspended ports. If found, the Selective Suspend bit for the
port should be cleared; no other action is necessary.
upstream. Firmware should check for changes to the Enable
and Connect Registers. If a port has become disabled but is
still connected, an SE0 has been detected on the port. The
port should be treated as having been reset, and should be
reported to the host as newly connected.
When set to 1, Enable hardware upstream resume signal-
ing for connect/disconnect events during global resume.
When set to 0, Disable hardware upstream resume signal-
ing for connect/disconnect events during global resume.
Resume 4
Selective
Suspend
Port 4
R/W
R
3
0
3
0
Resume 3
Selective
Suspend
Port 3
R/W
R
2
0
2
0
Figure
Resume 2
Selective
Suspend
Port 2
. All bits in the register are
R/W
R
1
0
1
0
CY7C65113C
Address 0x4D
Address 0x4E
Resume 1
Page 30 of 48
Selective
Suspend
Port 1
R/W
R
0
0
0
0
[+] Feedback