CY7C65113C-SXC Cypress Semiconductor Corp, CY7C65113C-SXC Datasheet - Page 34

• Manufacturer Part Number: CY7C65113C-SXC
• Description: IC MCU 8K FULL SPEED USB 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 11
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-2259-5; CY7C65113C-SXC

Bits[5..0]: Byte Count.
Bit 6: Data Valid.
Bit 7: Data 0/1 Toggle.
Whenever the count updates from a SETUP or OUT transaction
on endpoint 0, the counter register locks and cannot be written
by the CPU. Reading the register unlocks it. This prevents
firmware from overwriting a status update on incoming SETUP
or OUT transactions before firmware has a chance to read the
data. Only endpoint 0 counter register is locked when updated.
The locking mechanism does not apply to the count registers of
other endpoints.
Document #: 38-08002 Rev. *F
These counter bits indicate the number of data bytes in a
transaction. For IN transactions, firmware loads the count
with the number of bytes to be transmitted to the host from
the endpoint FIFO. Valid values are 0 to 32, inclusive. For
OUT or SETUP transactions, the count is updated by hard-
ware to the number of data bytes received, plus two for the
CRC bytes. Valid values are 2 to 34, inclusive.
This bit is set on receiving a proper CRC when the end-
point FIFO buffer is loaded with data during transactions.
This bit is used OUT and SETUP tokens only. If the CRC
is not correct, the endpoint interrupt occurs, but Data Valid
is cleared to a zero.
This bit selects the DATA packet’s toggle state: 0 for
DATA0, 1 for DATA1. For IN transactions, firmware must
set this bit to the desired state. For OUT or SETUP trans-
actions, the hardware sets this bit to the state of the re-
ceived Data Toggle bit.
Endpoint Mode/Count Registers Update and Locking
Mechanism
The contents of the endpoint mode and counter registers are
updated, based on the packet flow diagram. Two time points,
SETUP and UPDATE, are shown in the same figure. The
following activities occur at each time point:
SETUP:
The SETUP bit of the endpoint 0 mode register is forced HIGH
at this time. This bit is forced HIGH by the SIE until the end of the
data phase of a control write transfer. The SETUP bit can not be
cleared by firmware during this time.
The affected mode and counter registers of endpoint 0 are
locked from any CPU writes once they are updated. These
registers can be unlocked by a CPU read, only if the read
operation occurs after the UPDATE. The firmware needs to
perform a register read as a part of the endpoint ISR processing
to unlock the effected registers. The locking mechanism on
mode and counter registers ensures that the firmware recog-
nizes the changes that the SIE might have made since the
previous IO read of that register.
UPDATE:
1. Endpoint Mode Register – All the bits are updated (except the
2. Counter Registers – All bits are updated.
3. Interrupt – If an interrupt is to be generated as a result of the
4. The contents of the updated endpoint 0 mode and counter
SETUP bit of the endpoint 0 mode register).
transaction, the interrupt flag for the corresponding endpoint
is set at this time. For details on what conditions are required
to generate an endpoint interrupt, refer to
registers are locked, except the SETUP bit of the endpoint 0
mode register which was locked earlier.
CY7C65113C
Table
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