CY7C65113C-SXC Cypress Semiconductor Corp, CY7C65113C-SXC Datasheet - Page 31

• Manufacturer Part Number: CY7C65113C-SXC
• Description: IC MCU 8K FULL SPEED USB 28-SOIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C65113C-SXC

• Applications: USB Hub/Microcontroller
• Core Processor: M8
• Program Memory Type: OTP (8 kB)
• Controller Series: USB Hub
• Ram Size: 256 x 8
• Interface: I²C, USB
• Number Of I /o: 11
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 28-SOIC (7.5mm Width)
• Controller Family/series: (8051) USB
• No. Of I/o's: 11
• Ram Memory Size: 256Byte
• Cpu Speed: 48MHz
• No. Of Timers: 1
• Digital Ic Case Style: SOIC
• Core Size: 8 Bit
• Program Memory Size: 8KB
• Embedded Interface Type: I2C, USB
• Rohs Compliant: Yes
• Processor Series: CY7C65xx
• Core: M8
• Data Bus Width: 16 bit
• Data Ram Size: 256 B
• Interface Type: I2C
• Maximum Clock Frequency: 12 MHz
• Number Of Programmable I/os: 11
• Number Of Timers: 1
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: CY3654, CY3654-P03
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3649 - PROGRAMMER HI-LO USB M8428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Details
• Other names: 428-2259-5; CY7C65113C-SXC

Bits[2..0]: Control Action
Table 9. Control Bit Definition for Upstream Port
Bit 3: Bus Activity.
Bits 4 and 5: D– Upstream and D+ Upstream.
Bit 6: Endpoint Mode.
Bit 7: Endpoint Size.
Document #: 38-08002 Rev. *F
Control Bits
USB Status and Control
Bit #
Bit Name
Read/Write
Reset
USB Device Address (Device A, B)
Bit #
Bit Name
Read/Write
Reset
Set to control action as per
USB operation, all of these bits must be cleared.
This is a “sticky” bit that indicates if any non-idle USB event
has occurred on the upstream USB port. Firmware should
check and clear this bit periodically to detect any loss of
bus activity. Writing a ‘0’ to the Bus Activity bit clears it,
while writing a ‘1’ preserves the current value. In other
words, the firmware can clear the Bus Activity bit, but only
the SIE can set it.
These bits give the state of each upstream port pin individ-
ually: 1 = HIGH, 0 = LOW.
This bit used to configure the number of USB endpoints.
See Section for a detailed description.
This bit used to configure the number of USB endpoints.
See Section for a detailed description.
000
001
010
100
101
011
110
111
Not Forcing (SIE Controls Driver)
Force D+[0] HIGH, D–[0] LOW
Force D+[0] LOW, D–[0] HIGH
Force SE0; D+[0] LOW, D–[0] LOW
Force D+[0] LOW, D–[0] LOW
Force D+[0] HiZ, D–[0] LOW
Force D+[0] LOW, D–[0] HiZ
Force D+[0] HiZ, D–[0] HiZ
Endpoint
Address
Device
Enable
Size
R/W
R/W
7
0
7
0
Table
Endpoint
Address
Device
Mode
Control Action
Bit 6
R/W
R/W
6
0
6
0
9. The three control bits allow the upstream port to be driven manually by firmware. For normal
Figure 31. USB Status and Control Register.
Figure 32. USB Device Address Registers
Upstream
Address
Device
Bit 5
R/W
D+
R
5
0
5
0
Table 9
Upstream
Address
Device
shows how the control bits affect the upstream port.
Bit 4
R/W
D–
R
4
0
4
0
The hub generates an EOP at EOF1 in accordance with the USB
1.1 Specification, Section 11.2.2 as well as USB 2.0 specification
(section 11.2.5, page 304).
USB Serial Interface Engine Operation
The CY7C65113C SIE supports operation as a single device or
a compound device. This section describes the two device
addresses, the configurable endpoints, and the endpoint
function.
USB Device Addresses
The USB Controller provides two USB Device Address
Registers: A (addressed at 0x10)and B (addressed at 0x40).
Upon reset and under default conditions, Device A has three
endpoints and Device B has two endpoints. The USB Device
Address Register contents are cleared during a reset, setting the
USB device addresses to zero and disabling these addresses.
Figure 32
Bus Activity
Address
Device
Bit 3
R/W
R/W
shows the format of the USB Address Registers.
3
0
3
0
Address
Control
Device
Action
Bit 2
R/W
Bit 2
R/W
2
0
2
0
Addresses 0x10(A) and 0x40(B)
Address
Control
Device
Action
Bit 1
R/W
Bit 1
R/W
1
0
1
0
CY7C65113C
Address 0x1F
Page 31 of 48
Address
Control
Device
Action
Bit 0
R/W
Bit 0
R/W
0
0
0
0
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