MC68SEC000AA16 Freescale Semiconductor, MC68SEC000AA16 Datasheet - Page 120

• Manufacturer Part Number: MC68SEC000AA16
• Description: IC MPU 32BIT 16MHZ 64-QFP
• Manufacturer: Freescale Semiconductor
• Series: M68000r

Specifications of MC68SEC000AA16

• Processor Type: M680x0 32-Bit
• Speed: 16MHz
• Voltage: 3.3V, 5V
• Mounting Type: Surface Mount
• Package / Case: 64-QFP
• Processor Series: M680xx
• Core: CPU32
• Maximum Clock Frequency: 16 MHz
• Operating Supply Voltage: 3.3 V, 5 V
• Maximum Operating Temperature: + 105 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: 0 C
• Core Size: 32 Bit
• Cpu Speed: 16MHz
• Digital Ic Case Style: QFP
• No. Of Pins: 64
• Supply Voltage Range: 5V
• Operating Temperature Range: 0°C To +70°C
• Frequency Typ: 20MHz
• Filter Terminals: SMD
• Rohs Compliant: Yes
• Clock Frequency: 16MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

8.4 Clock Phase and Polarity Controls
Software can select one of four combinations of serial clock phase and polarity using two bits in the SPI
control register (SPCR). The clock polarity is specified by the CPOL control bit, which selects an active
high or active low clock, and has no significant effect on the transfer format. The clock phase (CPHA)
control bit selects one of two different transfer formats. The clock phase and polarity should be identical
for the master SPI device and the communicating slave device. In some cases, the phase and polarity
are changed between transfers to allow a master device to communicate with peripheral slaves having
different requirements.
When CPHA equals 0, the SS line must be negated and reasserted between each successive serial byte.
Also, if the slave writes data to the SPI data register (SPDR) while SS is low, a write collision error results.
When CPHA equals 1, the SS line can remain low between successive transfers.
120
Serial Peripheral Interface (SPI)
÷2 ÷4 ÷16 ÷32
MCU CLOCK
INTERNAL
SELECT
DIVIDER
SPI STATUS REGISTER
SPI CONTROL
SPI INTERRUPT
REQUEST
M68HC11E Family Data Sheet, Rev. 5.1
Figure 8-1. SPI Block Diagram
MSB
8--BIT SHIFT REGISTER
INTERNAL
DATA BUS
MSTR
SPE
READ DATA BUFFER
SPI CONTROL REGISTER
CLOCK
LOGIC
LSB
CLOCK
S
M
M
S
S
M
Freescale Semiconductor
MISO
MOSI
PD2
PD3
SCK
PD4
PD5
SS