MC68060RC50 Freescale Semiconductor, MC68060RC50 Datasheet - Page 222

IC MPU 32BIT 50MHZ 206-PGA

MC68060RC50

Manufacturer Part Number
MC68060RC50
Description
IC MPU 32BIT 50MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Datasheets

Specifications of MC68060RC50

Processor Type
M680x0 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 110C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
206
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC68060RC50
Manufacturer:
MOTO
Quantity:
5 530
Part Number:
MC68060RC50A
Manufacturer:
AEROFLE
Quantity:
220
Part Number:
MC68060RC50C
Manufacturer:
MOTO
Quantity:
5 530
Part Number:
MC68060RC50C
Manufacturer:
MOTO
Quantity:
5 530
Part Number:
MC68060RC50C
Manufacturer:
SAMSUNG
Quantity:
5 704
Figure 7-44 illustrates a functional timing diagram for an arbitration of a relinquish and retry
operation (MC68040 acknowledge termination mode). In Figure 7-44, the processor read
access that begins in C1 is terminated at the end of C2 with a retry request and BG negated,
forcing the processor to relinquish the bus and allow the alternate master to access the bus.
Note that the processor re-asserts BR during C3 since the original access is pending again.
After alternate bus master ownership, the bus is granted to the processor to allow it to retry
the access beginning in C7.
Figure 7-45 is a functional timing diagram for implicit ownership of the bus.
Figure 7-46 illustrates the effect of BGR on bus arbitration activity during locked sequences.
When BGR is asserted while BG is negated, locked sequences can be broken. Otherwise,
the entire locked sequence of bus cycles are completed by the processor before relinquish-
ing the bus.
MOTOROLA
ARBITRATION
ATTRIBUTES
* AM indicates the alternate bus master.
TRANSFER
D31–D0
A31–A0
AM_BG*
AM_BR*
STATE
BCLK
BUS
BTT
BR
BG
TA
BB
TS
AM-EX
C1
ALTERNATE
MASTER
Figure 7-43. Processor Bus Request Timing
AM-EX
C2
AM-EX
C3
M68060 USER’S MANUAL
EX-OWN
C4
EX-OWN
C5
PROCESSOR
EX-OWN
C6
EX-OWN
C7
END-TEN
C8
AM-IMP
C9
ALTERNATE
MASTER
Bus Operation
AM-EX
C10
7-67

Related parts for MC68060RC50