MC68060RC50 Freescale Semiconductor, MC68060RC50 Datasheet - Page 99

• Manufacturer Part Number: MC68060RC50
• Description: IC MPU 32BIT 50MHZ 206-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68060RC50

• Processor Type: M680x0 32-Bit
• Speed: 50MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 206-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 50MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 3.3V
• Operating Supply Voltage (max): 3.465V
• Operating Supply Voltage (min): 3.135V
• Operating Temp Range: 0C to 110C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 206
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Memory Management Unit
4.6.2 Effect of MDIS on Address Translation
The assertion of MDIS prevents the MMUs from performing ATC searches and the execu-
tion unit from performing table searches. With address translation disabled, logical
addresses are used as physical addresses. MDIS disables the MMUs on the next internal
access boundary when asserted and enables the MMUs on the next boundary after the sig-
nal is negated. The assertion of this signal does not affect the operation of the transparent
translation registers or execution of the PFLUSH instruction.
4.7 MMU INSTRUCTIONS
The MC68060 instruction set includes three privileged instructions that perform MMU oper-
ations. The following paragraphs briefly describe each of these instructions. For detailed
descriptions of these instructions, refer to M68000PR/AD, M68000 Family Programmer's
Reference Manual .
4.7.1 MOVEC
The MOVEC instruction transfers data between an integer data register and any of the
MC68060 control and status registers. The operating system uses the MOVEC instruction
to control and monitor MMU operation by manipulating and reading the seven MMU regis-
ters.
4.7.2 PFLUSH
The PFLUSH instruction invalidates (flushes) address translation descriptors in the speci-
fied ATC(s). PFLUSHA, a version of the PFLUSH instruction, flushes all entries. The
PFLUSH instruction flushes a user or supervisor entry with a specified logical address. The
PFLUSHAN and PFLUSHN instruction variants qualify entry selection further by flushing
only entries that are nonglobal, indicated by a cleared G-bit in the entry.
4.7.3 PLPA
The PLPA instruction ensures that an ATC is loaded with a valid translation, and returns the
related physical address. If there is a hit in the ATC, and the access has write and supervisor
privilege as specified, the PLPA returns the related physical address. If the PLPA misses in
the ATC, a table search is performed. A successful table search results in the ATC being
loaded with a valid translation; a table search which encounters an invalid descriptor, write-
protection violation, bus error or a supervisor violation will cause the access error exception
to be taken. There are two variants of PLPA, which are PLPAR and PLPAW, which check
the privilege and set the table and ATC history bits as if a read or write access, respectively,
were being performed.
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M68060 USER’S MANUAL
MOTOROLA