MC68060RC50 Freescale Semiconductor, MC68060RC50 Datasheet - Page 315
![IC MPU 32BIT 50MHZ 206-PGA](/photos/6/77/67732/mc68060rc50_sml.jpg)
MC68060RC50
Manufacturer Part Number
MC68060RC50
Description
IC MPU 32BIT 50MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68060RC50
Processor Type
M680x0 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 110C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
206
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
Quantity
Price
Company:
Part Number:
MC68060RC50
Manufacturer:
MOTO
Quantity:
5 530
Company:
Part Number:
MC68060RC50C
Manufacturer:
MOTO
Quantity:
5 530
Company:
Part Number:
MC68060RC50C
Manufacturer:
MOTO
Quantity:
5 530
Company:
Part Number:
MC68060RC50C
Manufacturer:
SAMSUNG
Quantity:
5 704
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10.9 SHIFT/ROTATE EXECUTION TIMES
Table 10-13 indicates the number of clock cycles required for execution of the shift and
rotate instructions. The number of operand read and write cycles is shown in parentheses
(r/w). Where indicated, the number of clock cycles and r/w cycles must be added to those
required for effective address calculation.
10.10 BIT MANIPULATION AND BIT FIELD EXECUTION TIMES
Table 10-14 and Table 10-15 indicate the number of clock cycles required for execution of
the bit manipulation instructions. The execution times for the bit field instructions is shown
in Table 10-16. The number of operand read and write cycles is shown in parentheses (r/w).
Where indicated, the number of clock cycles and r/w cycles must be added to those required
for effective address calculation.
MOTOROLA
1
For entries in this column, add the effective address calculation time. These operations
are word-size only.
ROXL, ROXR
Instruction
ROL, ROR
ASL, ASR
LSL, LSR
Table 10-14. Bit Manipulation (Dynamic Bit Count)
1
For entries in this column, add the effective address calculation
time.
“
“
“
“
Instruction
Table 10-13. Shift/Rotate Execution Times
BCHG
BCLR
BSET
BTST
“
“
“
“
M68060 USER’S MANUAL
Execution Times
Byte, Word
Byte, Word
Byte, Word
Byte, Word
Long
Long
Long
Long
Byte
Byte
Byte
Byte
Size
Long
Long
Long
Long
Size
Register
1(0/0)
1(0/0)
1(0/0)
1(0/0)
—
—
—
—
Register
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
Memory
1(1/1)
1(1/1)
1(1/1)
1(1/0)
Instruction Execution Timing
—
—
—
—
Memory
1
1(1/1)
1(1/1)
1(1/1)
1(1/1)
—
—
—
—
1
10-19
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