MC68060RC50 Freescale Semiconductor, MC68060RC50 Datasheet - Page 320
MC68060RC50
Manufacturer Part Number
MC68060RC50
Description
IC MPU 32BIT 50MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68060RC50
Processor Type
M680x0 32-Bit
Speed
50MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
50MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 110C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
206
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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Quantity
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FABS
FDABS
FSABS
FADD
FDADD
FSADD
FCMP
FDIV
FDDIV
FSDIV
FMOVE
,FPx
FDMOVE
,FPx
FSMOVE
,FPx
FMOVE
FPy,
FMOVE
,FPCR
FMOVE
FPCR,
FINT
FINTRZ
Instruction
Instruction Execution Timing
10.15 FPU INSTRUCTION EXECUTION TIMES
Table 10-25 shows the number of clock cycles required for execution of the floating-point
instructions, including completion of the operation and storing of the result. The number of
operand read and write cycles is shown in parentheses (r/w).
10-24
1
2
PLPA (ATC hit)
PLPA (ATC miss)
PFLUSH
PFLUSHN
PFLUSHAN
PFLUSHA
RESET
STOP
SWAP
TRAPF
TRAPcc
TRAPV
UNLK
UNPK
For these entries, add the effective address calculation time.
For the CPUSH instruction, the operand write figure refers to line-sized transfers.
Table 10-24. Miscellaneous Instruction Execution Times (Continued)
37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0)
37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0)
37(0/0) 39(0/0) 37(1/0) 37(1/0) 37(1/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
3(0/0)
3(0/0)
3(0/0)
1(0/0)
3(0/0)
3(0/0)
FPn
—
—
—
Instruction
Table 10-25. Floating-Point Instruction Execution Times
3(0/0)
3(0/0)
3(0/0)
5(0/0)
5(0/0)
5(0/0)
3(0/0)
3(0/0)
3(0/0)
3(0/0)
3(0/0)
8(0/0)
4(0/0)
4(0/0)
4(0/0)
Dn
1(1/0)
1(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(0/1)
6(1/0)
2(0/1)
3(1/0)
3(1/0)
(An)
Word
Word
(An)+
1(1/0)
1(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(0/1)
6(1/0)
2(0/1)
3(1/0)
3(1/0)
Size
—
—
—
—
—
—
—
—
—
—
—
—
M68060 USER’S MANUAL
Register
520(0/0)
15(0/0)
28(0/0)
18(0/0)
18(0/0)
33(0/0)
33(0/0)
8(0/0)
1(0/0)
1(0/0)
1(0/0)
1(0/0)
1(1/0)
2(0/0)
1(1/0)
1(1/0)
3(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(0/1)
6(1/0)
2(0/1)
3(1/0)
–(An)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
Effective Address, <ea>
(d16,An)
(d16,PC)
37(1/0)
37(1/0)
37(1/0)
1(1/0)
1(1/0)
1(1/0)
3(1/0)
3(1/0)
3(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
1(1/0)
6(1/0)
2(1/0)
3(1/0)
3(1/0)
Memory
2(1/1)
—
—
—
—
—
—
—
—
—
—
—
—
—
(d8,PC,Xi SF)
(d8,An,Xi SF)
38(1/0)
38(1/0)
38(1/0)
2(0/1)
7(1/0)
3(0/1)
2(1/0)
2(1/0)
2(1/0)
4(1/0)
4(1/0)
4(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
3(1/0)
Reg -> Dest
—
—
—
—
—
—
(bd,PC,XI SF)
—
—
—
—
—
—
—
—
(bd,An,XI SF)
39(1/0)
39(1/0)
39(1/0)
3(1/0)
3(1/0)
3(1/0)
3(0/1)
8(1/0)
4(0/1)
3(1/0)
3(1/0)
3(1/0)
5(1/0)
5(1/0)
5(1/0)
3(1/0)
5(1/0)
5(1/0)
Source -> Reg
(xxx).WL #<imm>
—
—
—
—
—
—
—
—
—
—
—
—
—
—
38(1/0)
38(1/0)
38(1/0)
2(0/1)
7(1/0)
3(0/1)
2(1/0)
2(1/0)
2(1/0)
4(1/0)
4(1/0)
4(1/0)
2(1/0)
2(1/0)
2(1/0)
2(1/0)
3(1/0)
3(1/0)
MOTOROLA
38(0/0)
38(0/0)
38(0/0)
1(0/0)
1(0/0)
1(0/0)
7(0/0)
2(0/0)
2(0/0)
2(0/0)
4(0/0)
4(0/0)
4(0/0)
2(0/0)
3(0/0)
3(0/0)
—
—
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