GCIXP1200GB Intel, GCIXP1200GB Datasheet - Page 14

• Manufacturer Part Number: GCIXP1200GB
• Description: IC MPU NETWORK 200MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GB

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839428

Intel
14
Table 1.
Table 2.
Table 3.
Table 4.
®
IXP1200 Network Processor
care” for these trailing bus cycles, except in the case of a status transfer where the IX Bus burst
includes a possible status transfer if the device were programmed to support it. Slave devices must
drive valid logic levels on the FDAT data pins during these cycles.
The tables below show the number of total IX Bus data cycles that will occur for a burst with
EOP/EOP_RX asserted at specific clocks for 64-bit and 32-bit IX Bus modes. In each case, the
tables show IX Bus cycles with and without the optional status transfer cycle. Refer to the IX Bus
Protocol Timing diagrams
64-bit IX Bus Receive Remainder Cycles, No Status Transfer
64-bit IX Bus Receive Remainder Cycles, with Status Transfer
32-bit IX Bus Receive Remainder Cycles, No Status Transfer
32-bit IX Bus Receive Remainder Cycles, with Status Transfer
# of bus cycles in burst:
# of Don’t Care cycles:
# of bus cycles in burst:
Status transfer
# of Don’t Care cycles:
NOTE:
# of bus cycles in burst:
# of Don’t Care cycles:
EOP/EOP_RX signaled on
# of bus cycles in burst:
Status
transfer
# of Don’t Care cycles:
NOTE:
EOP/EOP_RX signaled on
EOP/EOP_RX signaled on
EOP/EOP_RX signaled on
1. Status transfer occurs on a subsequent IX Bus status cycle.
1. Status transfer occurs on one or two subsequent IX Bus cycles.
this cycle:
this cycle:
this cycle:
this cycle:
32-bit status
64-bit status
(Figure 21
1
5
1
2
3
1
5
4
1
5
4
1
5
1
3
2
6
1
2
3
6
2
4
3
7
1
2
3
3
7
4
through
2
6
4
2
6
1
3
4
8
1
2
3
4
8
4
5
9
1
2
3
Figure
5
9
4
3
7
4
3
7
1
3
10
10
6
1
2
3
6
4
54) when interpreting these tables.
11
11
7
1
2
3
7
4
4
8
4
4
8
1
3
12
12
8
1
2
3
8
4
13
13
9
1
2
3
9
4
5
8
3
5
8
1
2
10
14
10
14
1
2
3
4
11
15
15
11
1
2
3
4
6
8
2
6
8
1
1
12
16
12
16
1
2
3
4
13
16
13
16
1
2
2
3
7
8
1
7
8
1
0
14
16
Datasheet
14
16
1
2
1
2
15
16
15
16
1
2
0
Note 1
1
8
8
0
8
8
0
16
16
N
16
16
o
e
1
0
t
0