GCIXP1200GB Intel, GCIXP1200GB Datasheet - Page 16

• Manufacturer Part Number: GCIXP1200GB
• Description: IC MPU NETWORK 200MHZ 432-BGA
• Manufacturer: Intel

Specifications of GCIXP1200GB

• Rohs Status: RoHS non-compliant
• Processor Type: Network
• Features: 32-bit StrongARM RISC Core
• Speed: 200MHz
• Voltage: 3.3V
• Mounting Type: Surface Mount
• Package / Case: 432-BGA
• Mounting: Surface Mount
• Operating Temperature (max): 70C
• Operating Temperature (min): 0C
• Operating Temperature Classification: Commercial
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 839428

Intel
5.4.1
16
Figure 3. SDRAM Unit Block Diagram
®
IXP1200 Network Processor
SDRAM Unit
The IXP1200 provides an SDRAM Unit to access low cost, high bandwidth memory for mass data
storage. The StrongARM* core address space allows up to 256 Mbytes of SDRAM to be
addressed. The SDRAM interface operates at half the core frequency (0.5*F
bandwidth of 928 Mbytes per second at 232 MHz.
Bus cycles are generated by requests from the PCI Unit including PCI DMA cycles, the
StrongARM* core, and the Microengines.
The SDRAM is operated by commands that are loaded into command queues within the unit. The
SDRAM Unit decodes the command, reads or writes the data, then deletes the command from the
head of the queue. The read and write sources may be SDRAM memory locations, transfer
registers, or the Transmit and Receive FIFOs in the FBI Unit. Refer to the IXP1200 Network
Processor Family Hardware Reference Manual for details on how these requests are queued,
prioritized, and serviced by the SDRAM Unit.
SDRAM should have an access time (t
Figure 3
The SDRAM Bus consists of 15 row/column address bits, 64 data bits, RAS#, CAS#, write enable,
DQM control, and a synchronous output clock running at one-half the IXP1200 core frequency
(0.5*F
The PCI, Microengines, and StrongARM* core require single byte, word, and longword write
capabilities. The SDRAM Unit supports this using a read-modify-write technique. As data is
written from the PCI or StrongARM* core to SDRAM, a quadword is read from SDRAM. The
* StrongARM is a registered trademark of ARM Limited.
** ARM architecture compatible
SDRAM
256 MB
core
up to
details the major components of the SDRAM Unit.
).
WE#,RAS#
CAS#, DQM
Data[63:0]
SDCLK
Adr[14:0]
Interface
SDRAM
Pin
data
addr
ac
) of 6 ns or less (CAS latency = 2), PC100 compatible.
& Address
Command
Generator
Decoder
Microengine Data [63:0]
Machine & Registers
Service Priority
(Arbitration)
AMBA Data
Memory/
FIFO
Microengine Address
& Command Queues
AMBA Address
(High Priority, Even,
RD/Wr Queue
Rd/Wr Queue
PCI Address
Odd & Order)
AMBA Bus
Interface
Logic
core
), providing a peak
(from
StrongARM
Core)
AMBA[31:0]
PCI Commands
and Addresses
Microengine
Commands &
Addresses
Datasheet
A7013-03
®
*